diff options
| -rw-r--r-- | pyGHDL/dom/Sequential.py | 6 | ||||
| -rw-r--r-- | pyGHDL/dom/_Translate.py | 8 | ||||
| -rw-r--r-- | testsuite/pyunit/Current.vhdl | 1 |
3 files changed, 8 insertions, 7 deletions
diff --git a/pyGHDL/dom/Sequential.py b/pyGHDL/dom/Sequential.py index 70a16e4cd..372939b28 100644 --- a/pyGHDL/dom/Sequential.py +++ b/pyGHDL/dom/Sequential.py @@ -424,11 +424,11 @@ class SequentialProcedureCall(VHDLModel_SequentialProcedureCall, DOMMixin): def parse(cls, callNode: Iir, label: str) -> "SequentialProcedureCall": from pyGHDL.dom._Translate import GetNameFromNode, GetParameterMapAspect - call = nodes.Get_Procedure_Call(callNode) + cNode = nodes.Get_Procedure_Call(callNode) - prefix = nodes.Get_Prefix(call) + prefix = nodes.Get_Prefix(cNode) procedureName = GetNameFromNode(prefix) - parameterAssociations = GetParameterMapAspect(nodes.Get_Parameter_Association_Chain(callNode)) + parameterAssociations = GetParameterMapAspect(nodes.Get_Parameter_Association_Chain(cNode)) return cls(callNode, procedureName, parameterAssociations, label) diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 5322760ab..9fe6e9ddd 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -41,7 +41,9 @@ from pyGHDL.dom.Sequential import ( SequentialReportStatement, SequentialAssertStatement, WaitStatement, - SequentialSimpleSignalAssignment, NullStatement, + SequentialSimpleSignalAssignment, + NullStatement, + SequentialProcedureCall, ) from pyVHDLModel.SyntaxModel import ( ConstraintUnion, @@ -967,9 +969,7 @@ def GetSequentialStatementsFromChainedNodes( elif kind == nodes.Iir_Kind.Wait_Statement: yield WaitStatement.parse(statement, label) elif kind == nodes.Iir_Kind.Procedure_Call_Statement: - print( - "[NOT IMPLEMENTED] Procedure call (label: '{label}') at line {line}".format(label=label, line=pos.Line) - ) + yield SequentialProcedureCall.parse(statement, label) elif kind == nodes.Iir_Kind.Report_Statement: yield SequentialReportStatement.parse(statement, label) elif kind == nodes.Iir_Kind.Assertion_Statement: diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index c02493c21..c7ce678b3 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -94,6 +94,7 @@ begin Q <= D after 10 ns; else Q <= std_logic_vector(unsigned(Q) + 1); + counter.increment(1); end if; end if; |