diff options
| -rw-r--r-- | testsuite/synth/synth109/asymmetric_ram_2a.vhd | 113 | ||||
| -rw-r--r-- | testsuite/synth/synth109/asymmetric_ram_2b.vhd | 126 | ||||
| -rw-r--r-- | testsuite/synth/synth109/ram1.vhdl | 38 | ||||
| -rw-r--r-- | testsuite/synth/synth109/ram2.vhdl | 60 | ||||
| -rw-r--r-- | testsuite/synth/synth109/ram3.ghw | bin | 0 -> 1341 bytes | |||
| -rw-r--r-- | testsuite/synth/synth109/ram3.vhdl | 70 | ||||
| -rw-r--r-- | testsuite/synth/synth109/ram4.vhdl | 47 | ||||
| -rw-r--r-- | testsuite/synth/synth109/ram9.vhdl | 104 | ||||
| -rw-r--r-- | testsuite/synth/synth109/tb_ram1.vhdl | 62 | ||||
| -rw-r--r-- | testsuite/synth/synth109/tb_ram2.vhdl | 91 | ||||
| -rw-r--r-- | testsuite/synth/synth109/tb_ram4.vhdl | 62 | ||||
| -rw-r--r-- | testsuite/synth/synth109/tb_ram9.vhdl | 80 | ||||
| -rwxr-xr-x | testsuite/synth/synth109/testsuite.sh | 13 |
13 files changed, 866 insertions, 0 deletions
diff --git a/testsuite/synth/synth109/asymmetric_ram_2a.vhd b/testsuite/synth/synth109/asymmetric_ram_2a.vhd new file mode 100644 index 000000000..3f8922f9f --- /dev/null +++ b/testsuite/synth/synth109/asymmetric_ram_2a.vhd @@ -0,0 +1,113 @@ +-- +-- Asymmetric port RAM +-- Port A is 256x8-bit read-and-write (write-first synchronization) +-- Port B is 64x32-bit read-and-write (write-first synchronization) +-- +-- Download: ftp://ftp.xilinx.com/pub/documentation/misc/xstug_examples.zip +-- File: HDL_Coding_Techniques/rams/asymmetric_ram_2a.vhd +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +entity asymmetric_ram_2a is + + generic ( + WIDTHA : integer := 8; + SIZEA : integer := 256; + ADDRWIDTHA : integer := 8; + WIDTHB : integer := 32; + SIZEB : integer := 64; + ADDRWIDTHB : integer := 6 + ); + + port ( + clkA : in std_logic; + clkB : in std_logic; + enA : in std_logic; + enB : in std_logic; + weA : in std_logic; + weB : in std_logic; + addrA : in std_logic_vector(ADDRWIDTHA-1 downto 0); + addrB : in std_logic_vector(ADDRWIDTHB-1 downto 0); + diA : in std_logic_vector(WIDTHA-1 downto 0); + diB : in std_logic_vector(WIDTHB-1 downto 0); + doA : out std_logic_vector(WIDTHA-1 downto 0); + doB : out std_logic_vector(WIDTHB-1 downto 0) + ); + +end asymmetric_ram_2a; + +architecture behavioral of asymmetric_ram_2a is + + function max(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + + function min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + constant minWIDTH : integer := min(WIDTHA,WIDTHB); + constant maxWIDTH : integer := max(WIDTHA,WIDTHB); + constant maxSIZE : integer := max(SIZEA,SIZEB); + constant RATIO : integer := maxWIDTH / minWIDTH; + + type ramType is array (0 to maxSIZE-1) of std_logic_vector(minWIDTH-1 downto 0); + shared variable ram : ramType := (others => (others => '0')); + + signal readA : std_logic_vector(WIDTHA-1 downto 0):= (others => '0'); + signal readB : std_logic_vector(WIDTHB-1 downto 0):= (others => '0'); + signal regA : std_logic_vector(WIDTHA-1 downto 0):= (others => '0'); + signal regB : std_logic_vector(WIDTHB-1 downto 0):= (others => '0'); + +begin + + process (clkA) + begin + if rising_edge(clkA) then + if enA = '1' then + if weA = '1' then + ram(conv_integer(addrA)) := diA; + end if; + readA <= ram(conv_integer(addrA)); + end if; + regA <= readA; + end if; + end process; + + process (clkB) + begin + if rising_edge(clkB) then + if enB = '1' then + if weB = '1' then + ram(conv_integer(addrB&conv_std_logic_vector(0,2))) := diB(minWIDTH-1 downto 0); + ram(conv_integer(addrB&conv_std_logic_vector(1,2))) := diB(2*minWIDTH-1 downto minWIDTH); + ram(conv_integer(addrB&conv_std_logic_vector(2,2))) := diB(3*minWIDTH-1 downto 2*minWIDTH); + ram(conv_integer(addrB&conv_std_logic_vector(3,2))) := diB(4*minWIDTH-1 downto 3*minWIDTH); + end if; + readB(minWIDTH-1 downto 0) <= ram(conv_integer(addrB&conv_std_logic_vector(0,2))); + readB(2*minWIDTH-1 downto minWIDTH) <= ram(conv_integer(addrB&conv_std_logic_vector(1,2))); + readB(3*minWIDTH-1 downto 2*minWIDTH) <= ram(conv_integer(addrB&conv_std_logic_vector(2,2))); + readB(4*minWIDTH-1 downto 3*minWIDTH) <= ram(conv_integer(addrB&conv_std_logic_vector(3,2))); + end if; + regB <= readB; + end if; + end process; + + doA <= regA; + doB <= regB; + +end behavioral; diff --git a/testsuite/synth/synth109/asymmetric_ram_2b.vhd b/testsuite/synth/synth109/asymmetric_ram_2b.vhd new file mode 100644 index 000000000..4a8663d20 --- /dev/null +++ b/testsuite/synth/synth109/asymmetric_ram_2b.vhd @@ -0,0 +1,126 @@ +-- +-- Asymmetric port RAM +-- Port A is 256x8-bit read-and-write (write-first synchronization) +-- Port B is 64x32-bit read-and-write (write-first synchronization) +-- Compact description with a for-loop statement +-- +-- Download: ftp://ftp.xilinx.com/pub/documentation/misc/xstug_examples.zip +-- File: HDL_Coding_Techniques/rams/asymmetric_ram_2b.vhd +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +entity asymmetric_ram_2b is + + generic ( + WIDTHA : integer := 8; + SIZEA : integer := 256; + ADDRWIDTHA : integer := 8; + WIDTHB : integer := 32; + SIZEB : integer := 64; + ADDRWIDTHB : integer := 6 + ); + + port ( + clkA : in std_logic; + clkB : in std_logic; + enA : in std_logic; + enB : in std_logic; + weA : in std_logic; + weB : in std_logic; + addrA : in std_logic_vector(ADDRWIDTHA-1 downto 0); + addrB : in std_logic_vector(ADDRWIDTHB-1 downto 0); + diA : in std_logic_vector(WIDTHA-1 downto 0); + diB : in std_logic_vector(WIDTHB-1 downto 0); + doA : out std_logic_vector(WIDTHA-1 downto 0); + doB : out std_logic_vector(WIDTHB-1 downto 0) + ); + +end asymmetric_ram_2b; + +architecture behavioral of asymmetric_ram_2b is + + function max(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + + function min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + function log2 (val: INTEGER) return natural is + variable res : natural; + begin + for i in 0 to 31 loop + if (val <= (2**i)) then + res := i; + exit; + end if; + end loop; + return res; + end function Log2; + + constant minWIDTH : integer := min(WIDTHA,WIDTHB); + constant maxWIDTH : integer := max(WIDTHA,WIDTHB); + constant maxSIZE : integer := max(SIZEA,SIZEB); + constant RATIO : integer := maxWIDTH / minWIDTH; + + type ramType is array (0 to maxSIZE-1) of std_logic_vector(minWIDTH-1 downto 0); + shared variable ram : ramType := (others => (others => '0')); + + signal readA : std_logic_vector(WIDTHA-1 downto 0):= (others => '0'); + signal readB : std_logic_vector(WIDTHB-1 downto 0):= (others => '0'); + signal regA : std_logic_vector(WIDTHA-1 downto 0):= (others => '0'); + signal regB : std_logic_vector(WIDTHB-1 downto 0):= (others => '0'); + +begin + + process (clkA) + begin + if rising_edge(clkA) then + if enA = '1' then + if weA = '1' then + ram(conv_integer(addrA)) := diA; + end if; + readA <= ram(conv_integer(addrA)); + end if; + regA <= readA; + end if; + end process; + + process (clkB) + begin + if rising_edge(clkB) then + if enB = '1' then + if weB = '1' then + for i in 0 to RATIO-1 loop + ram(conv_integer(addrB & conv_std_logic_vector(i,log2(RATIO)))) + := diB((i+1)*minWIDTH-1 downto i*minWIDTH); + end loop; + end if; + for i in 0 to RATIO-1 loop + readB((i+1)*minWIDTH-1 downto i*minWIDTH) + <= ram(conv_integer(addrB & conv_std_logic_vector(i,log2(RATIO)))); + end loop; + end if; + regB <= readB; + end if; + end process; + + doA <= regA; + doB <= regB; + +end behavioral; diff --git a/testsuite/synth/synth109/ram1.vhdl b/testsuite/synth/synth109/ram1.vhdl new file mode 100644 index 000000000..8fdbfbd5f --- /dev/null +++ b/testsuite/synth/synth109/ram1.vhdl @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ram1 is + generic ( + WIDTHB : integer := 32; + SIZEB : integer := 64; + ADDRWIDTHB : integer := 6 + ); + + port ( + clkB : in std_logic; + enB : in std_logic; + weB : in std_logic; + addrB : in std_logic_vector(ADDRWIDTHB-1 downto 0); + diB : in std_logic_vector(WIDTHB-1 downto 0); + doB : out std_logic_vector(WIDTHB-1 downto 0) + ); + +end ram1; + +architecture behavioral of ram1 is + type ramType is array (0 to SIZEB-1) of std_logic_vector(WIDTHB-1 downto 0); + shared variable ram : ramType := (others => (others => '0')); +begin + process (clkB) + begin + if rising_edge(clkB) then + if enB = '1' then + if weB = '1' then + ram(to_integer(unsigned(addrB))) := diB; + end if; + doB <= ram(to_integer(unsigned(addrB))); + end if; + end if; + end process; +end behavioral; diff --git a/testsuite/synth/synth109/ram2.vhdl b/testsuite/synth/synth109/ram2.vhdl new file mode 100644 index 000000000..11f093552 --- /dev/null +++ b/testsuite/synth/synth109/ram2.vhdl @@ -0,0 +1,60 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ram2 is + + generic ( + WIDTH : integer := 32; + SIZE : integer := 64; + ADDRWIDTH : integer := 6 + ); + + port ( + clkA : in std_logic; + clkB : in std_logic; + enA : in std_logic; + enB : in std_logic; + weA : in std_logic; + weB : in std_logic; + addrA : in std_logic_vector(ADDRWIDTH-1 downto 0); + addrB : in std_logic_vector(ADDRWIDTH-1 downto 0); + diA : in std_logic_vector(WIDTH-1 downto 0); + diB : in std_logic_vector(WIDTH-1 downto 0); + doA : out std_logic_vector(WIDTH-1 downto 0); + doB : out std_logic_vector(WIDTH-1 downto 0) + ); + +end ram2; + +library ieee; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +architecture behavioral of ram2 is + type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0); + shared variable ram : ramType := (others => (others => '0')); +begin + process (clkA) + begin + if rising_edge(clkA) then + if enA = '1' then + if weA = '1' then + ram(conv_integer(addrA)) := diA; + end if; + doA <= ram(conv_integer(addrA)); + end if; + end if; + end process; + + process (clkB) + begin + if rising_edge(clkB) then + if enB = '1' then + if weB = '1' then + ram(conv_integer(addrB)) := diB; + end if; + doB <= ram(conv_integer(addrB)); + end if; + end if; + end process; +end behavioral; diff --git a/testsuite/synth/synth109/ram3.ghw b/testsuite/synth/synth109/ram3.ghw Binary files differnew file mode 100644 index 000000000..8006162f2 --- /dev/null +++ b/testsuite/synth/synth109/ram3.ghw diff --git a/testsuite/synth/synth109/ram3.vhdl b/testsuite/synth/synth109/ram3.vhdl new file mode 100644 index 000000000..50a949d27 --- /dev/null +++ b/testsuite/synth/synth109/ram3.vhdl @@ -0,0 +1,70 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; + +entity ram2 is + + generic ( + WIDTH : integer := 32; + SIZE : integer := 64; + ADDRWIDTH : integer := 6 + ); + + port ( + clkA : in std_logic; + clkB : in std_logic; + enA : in std_logic; + enB : in std_logic; + weA : in std_logic; + weB : in std_logic; + addrA : in std_logic_vector(ADDRWIDTH-1 downto 0); + addrB : in std_logic_vector(ADDRWIDTH-1 downto 0); + diA : in std_logic_vector(WIDTH-1 downto 0); + diB : in std_logic_vector(WIDTH-1 downto 0); + doA : out std_logic_vector(WIDTH-1 downto 0); + doB : out std_logic_vector(WIDTH-1 downto 0) + ); + +end ram2; + +architecture behavioral of ram2 is + type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0); + shared variable ram : ramType := (others => (others => '0')); + + signal readA : std_logic_vector(WIDTH-1 downto 0):= (others => '0'); + signal readB : std_logic_vector(WIDTH-1 downto 0):= (others => '0'); + signal regA : std_logic_vector(WIDTH-1 downto 0):= (others => '0'); + signal regB : std_logic_vector(WIDTH-1 downto 0):= (others => '0'); + +begin + + process (clkA) + begin + if rising_edge(clkA) then + if enA = '1' then + if weA = '1' then + ram(conv_integer(addrA)) := diA; + end if; + readA <= ram(conv_integer(addrA)); + end if; + regA <= readA; + end if; + end process; + + process (clkB) + begin + if rising_edge(clkB) then + if enB = '1' then + if weB = '1' then + ram(conv_integer(addrB)) := diB; + end if; + readB <= ram(conv_integer(addrB)); + end if; + regB <= readB; + end if; + end process; + + doA <= regA; + doB <= regB; +end behavioral; diff --git a/testsuite/synth/synth109/ram4.vhdl b/testsuite/synth/synth109/ram4.vhdl new file mode 100644 index 000000000..134a55f4b --- /dev/null +++ b/testsuite/synth/synth109/ram4.vhdl @@ -0,0 +1,47 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ram4 is + + generic ( + WIDTHB : integer := 32; + SIZEB : integer := 64; + ADDRWIDTHB : integer := 6 + ); + + port ( + clkB : in std_logic; + enB : in std_logic; + weB : in std_logic; + addrB : in std_logic_vector(ADDRWIDTHB-1 downto 0); + diB : in std_logic_vector(WIDTHB-1 downto 0); + doB : out std_logic_vector(WIDTHB-1 downto 0) + ); + +end ram4; + +architecture behavioral of ram4 is + constant WIDTH : natural := WIDTHB / 4; + constant SIZE : natural := SIZEB * 4; + type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0); + shared variable ram : ramType := (others => (others => '0')); +begin + process (clkB) + begin + if rising_edge(clkB) then + if enB = '1' then + if weB = '1' then + ram(to_integer(unsigned(addrB)&"00")) := diB(WIDTH-1 downto 0); + ram(to_integer(unsigned(addrB)&"01")) := diB(2*WIDTH-1 downto WIDTH); + ram(to_integer(unsigned(addrB)&"10")) := diB(3*WIDTH-1 downto 2*WIDTH); + ram(to_integer(unsigned(addrB)&"11")) := diB(4*WIDTH-1 downto 3*WIDTH); + end if; + doB(WIDTH-1 downto 0) <= ram(to_integer(unsigned(addrB)&"00")); + doB(2*WIDTH-1 downto WIDTH) <= ram(to_integer(unsigned(addrB)&"01")); + doB(3*WIDTH-1 downto 2*WIDTH) <= ram(to_integer(unsigned(addrB)&"10")); + doB(4*WIDTH-1 downto 3*WIDTH) <= ram(to_integer(unsigned(addrB)&"11")); + end if; + end if; + end process; +end behavioral; diff --git a/testsuite/synth/synth109/ram9.vhdl b/testsuite/synth/synth109/ram9.vhdl new file mode 100644 index 000000000..30f324160 --- /dev/null +++ b/testsuite/synth/synth109/ram9.vhdl @@ -0,0 +1,104 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ram3 is + + generic ( + WIDTHA : integer := 8; + SIZEA : integer := 256; + ADDRWIDTHA : integer := 8; + WIDTHB : integer := 32; + SIZEB : integer := 64; + ADDRWIDTHB : integer := 6 + ); + + port ( + clkA : in std_logic; + clkB : in std_logic; + enA : in std_logic; + enB : in std_logic; + weA : in std_logic; + weB : in std_logic; + addrA : in std_logic_vector(ADDRWIDTHA-1 downto 0); + addrB : in std_logic_vector(ADDRWIDTHB-1 downto 0); + diA : in std_logic_vector(WIDTHA-1 downto 0); + diB : in std_logic_vector(WIDTHB-1 downto 0); + doA : out std_logic_vector(WIDTHA-1 downto 0); + doB : out std_logic_vector(WIDTHB-1 downto 0) + ); + +end ram3; + +architecture behavioral of ram3 is + + function max(L, R: INTEGER) return INTEGER is + begin + if L > R then + return L; + else + return R; + end if; + end; + + + function min(L, R: INTEGER) return INTEGER is + begin + if L < R then + return L; + else + return R; + end if; + end; + + constant minWIDTH : integer := min(WIDTHA,WIDTHB); + constant maxWIDTH : integer := max(WIDTHA,WIDTHB); + constant maxSIZE : integer := max(SIZEA,SIZEB); + constant RATIO : integer := maxWIDTH / minWIDTH; + + type ramType is array (0 to maxSIZE-1) of std_logic_vector(minWIDTH-1 downto 0); + shared variable ram : ramType := (others => (others => '0')); + + signal readA : std_logic_vector(WIDTHA-1 downto 0):= (others => '0'); + signal readB : std_logic_vector(WIDTHB-1 downto 0):= (others => '0'); + signal regA : std_logic_vector(WIDTHA-1 downto 0):= (others => '0'); + signal regB : std_logic_vector(WIDTHB-1 downto 0):= (others => '0'); + +begin + + process (clkA) + begin + if rising_edge(clkA) then + if enA = '1' then + if weA = '1' then + ram(to_integer(unsigned(addrA))) := diA; + end if; + readA <= ram(to_integer(unsigned(addrA))); + end if; + regA <= readA; + end if; + end process; + + process (clkB) + begin + if rising_edge(clkB) then + if enB = '1' then + if weB = '1' then + ram(to_integer(unsigned(addrB)&"00")) := diB(minWIDTH-1 downto 0); + ram(to_integer(unsigned(addrB)&"01")) := diB(2*minWIDTH-1 downto minWIDTH); + ram(to_integer(unsigned(addrB)&"10")) := diB(3*minWIDTH-1 downto 2*minWIDTH); + ram(to_integer(unsigned(addrB)&"11")) := diB(4*minWIDTH-1 downto 3*minWIDTH); + end if; + readB(minWIDTH-1 downto 0) <= ram(to_integer(unsigned(addrB)&"00")); + readB(2*minWIDTH-1 downto minWIDTH) <= ram(to_integer(unsigned(addrB)&"01")); + readB(3*minWIDTH-1 downto 2*minWIDTH) <= ram(to_integer(unsigned(addrB)&"10")); + readB(4*minWIDTH-1 downto 3*minWIDTH) <= ram(to_integer(unsigned(addrB)&"11")); + end if; + regB <= readB; + end if; + end process; + + doA <= regA; + doB <= regB; + +end behavioral; diff --git a/testsuite/synth/synth109/tb_ram1.vhdl b/testsuite/synth/synth109/tb_ram1.vhdl new file mode 100644 index 000000000..0d62d499f --- /dev/null +++ b/testsuite/synth/synth109/tb_ram1.vhdl @@ -0,0 +1,62 @@ +entity tb_ram1 is +end tb_ram1; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_ram1 is + signal clk : std_logic; + signal en : std_logic; + signal we : std_logic; + signal addr : std_logic_vector(5 downto 0); + signal rdat : std_logic_vector(31 downto 0); + signal wdat : std_logic_vector(31 downto 0); +begin + dut: entity work.ram1 + port map (clkB => clk, enB => en, weB => we, addrB => addr, + diB => wdat, doB => rdat); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + en <= '1'; + we <= '1'; + addr <= b"00_0000"; + wdat <= x"11_22_33_f0"; + pulse; + assert rdat = x"11_22_33_f0" severity failure; + + addr <= b"00_0001"; + wdat <= x"11_22_33_f1"; + pulse; + assert rdat = x"11_22_33_f1" severity failure; + + -- Read. + we <= '0'; + addr <= b"00_0000"; + wdat <= x"ff_22_33_f1"; + pulse; + assert rdat = x"11_22_33_f0" severity failure; + + addr <= b"00_0001"; + wdat <= x"ff_22_33_f1"; + pulse; + assert rdat = x"11_22_33_f1" severity failure; + + -- Disable. + en <= '0'; + we <= '1'; + addr <= b"00_0000"; + wdat <= x"11_22_33_f0"; + pulse; + assert rdat = x"11_22_33_f1" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/synth109/tb_ram2.vhdl b/testsuite/synth/synth109/tb_ram2.vhdl new file mode 100644 index 000000000..16a2d0af4 --- /dev/null +++ b/testsuite/synth/synth109/tb_ram2.vhdl @@ -0,0 +1,91 @@ +entity tb_ram2 is +end tb_ram2; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_ram2 is + signal clkA : std_logic; + signal enA : std_logic; + signal weA : std_logic; + signal addrA : std_logic_vector(5 downto 0); + signal rdatA : std_logic_vector(31 downto 0); + signal wdatA : std_logic_vector(31 downto 0); + + signal clkB : std_logic; + signal enB : std_logic; + signal weB : std_logic; + signal addrB : std_logic_vector(5 downto 0); + signal rdatB : std_logic_vector(31 downto 0); + signal wdatB : std_logic_vector(31 downto 0); +begin + dut: entity work.ram2 + port map (clkA => clkA, clkB => clkB, + enA => enA, enB => enB, + weA => weA, weB => weB, + addrA => addrA, addrB => addrB, + diA => wdatA, diB => wdatB, + doA => rdatA, doB => rdatB); + + process + procedure pulseB is + begin + clkB <= '0'; + wait for 1 ns; + clkB <= '1'; + wait for 1 ns; + end pulseB; + procedure pulseA is + begin + clkA <= '0'; + wait for 1 ns; + clkA <= '1'; + wait for 1 ns; + end pulseA; + begin + clkA <= '0'; + enA <= '0'; + + enB <= '1'; + weB <= '1'; + addrB <= b"00_0000"; + wdatB <= x"11_22_33_f0"; + pulseB; + assert rdatB = x"11_22_33_f0" severity failure; + + addrB <= b"00_0001"; + wdatB <= x"11_22_33_f1"; + pulseB; + assert rdatB = x"11_22_33_f1" severity failure; + + -- Read. + weB <= '0'; + addrB <= b"00_0000"; + wdatB <= x"ff_22_33_f1"; + pulseB; + assert rdatB = x"11_22_33_f0" severity failure; + + addrB <= b"00_0001"; + wdatB <= x"ff_22_33_f1"; + pulseB; + assert rdatB = x"11_22_33_f1" severity failure; + + -- Disable. + enB <= '0'; + weB <= '1'; + addrB <= b"00_0000"; + wdatB <= x"11_22_33_f0"; + pulseB; + assert rdatB = x"11_22_33_f1" severity failure; + + -- Read from A. + enA <= '1'; + weA <= '0'; + addrA <= b"00_0001"; + wdatA <= x"88_22_33_f1"; + pulseA; + assert rdatA = x"11_22_33_f1" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/synth109/tb_ram4.vhdl b/testsuite/synth/synth109/tb_ram4.vhdl new file mode 100644 index 000000000..8a20c9e7d --- /dev/null +++ b/testsuite/synth/synth109/tb_ram4.vhdl @@ -0,0 +1,62 @@ +entity tb_ram4 is +end tb_ram4; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_ram4 is + signal clk : std_logic; + signal en : std_logic; + signal we : std_logic; + signal addr : std_logic_vector(5 downto 0); + signal rdat : std_logic_vector(31 downto 0); + signal wdat : std_logic_vector(31 downto 0); +begin + dut: entity work.ram4 + port map (clkB => clk, enB => en, weB => we, addrB => addr, + diB => wdat, doB => rdat); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + en <= '1'; + we <= '1'; + addr <= b"00_0000"; + wdat <= x"11_22_33_f0"; + pulse; + assert rdat = x"11_22_33_f0" severity failure; + + addr <= b"00_0001"; + wdat <= x"11_22_33_f1"; + pulse; + assert rdat = x"11_22_33_f1" severity failure; + + -- Read. + we <= '0'; + addr <= b"00_0000"; + wdat <= x"ff_22_33_f1"; + pulse; + assert rdat = x"11_22_33_f0" severity failure; + + addr <= b"00_0001"; + wdat <= x"ff_22_33_f1"; + pulse; + assert rdat = x"11_22_33_f1" severity failure; + + -- Disable. + en <= '0'; + we <= '1'; + addr <= b"00_0000"; + wdat <= x"11_22_33_f0"; + pulse; + assert rdat = x"11_22_33_f1" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/synth109/tb_ram9.vhdl b/testsuite/synth/synth109/tb_ram9.vhdl new file mode 100644 index 000000000..6610b0f23 --- /dev/null +++ b/testsuite/synth/synth109/tb_ram9.vhdl @@ -0,0 +1,80 @@ +entity tb_ram3 is +end tb_ram3; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_ram3 is + signal clkA : std_logic; + signal enA : std_logic; + signal weA : std_logic; + signal addrA : std_logic_vector(7 downto 0); + signal rdatA : std_logic_vector(7 downto 0); + signal wdatA : std_logic_vector(7 downto 0); + + signal clkB : std_logic; + signal enB : std_logic; + signal weB : std_logic; + signal addrB : std_logic_vector(5 downto 0); + signal rdatB : std_logic_vector(31 downto 0); + signal wdatB : std_logic_vector(31 downto 0); +begin + dut: entity work.ram3 + port map (clkA => clkA, clkB => clkB, + enA => enA, enB => enB, + weA => weA, weB => weB, + addrA => addrA, addrB => addrB, + diA => wdatA, diB => wdatB, + doA => rdatA, doB => rdatB); + + process + procedure pulseB is + begin + clkB <= '0'; + wait for 1 ns; + clkB <= '1'; + wait for 1 ns; + end pulseB; + begin + clkA <= '0'; + enA <= '0'; + + enB <= '1'; + weB <= '1'; + addrB <= b"00_0000"; + wdatB <= x"11_22_33_f0"; + pulseB; + pulseB; + assert rdatB = x"11_22_33_f0" severity failure; + + addrB <= b"00_0001"; + wdatB <= x"11_22_33_f1"; + pulseB; + pulseB; + assert rdatB = x"11_22_33_f1" severity failure; + + -- Read. + weB <= '0'; + addrB <= b"00_0000"; + wdatB <= x"ff_22_33_f1"; + pulseB; + pulseB; + assert rdatB = x"11_22_33_f0" severity failure; + + addrB <= b"00_0001"; + wdatB <= x"ff_22_33_f1"; + pulseB; + pulseB; + assert rdatB = x"11_22_33_f1" severity failure; + + -- Disable. + enB <= '0'; + weB <= '1'; + addrB <= b"00_0000"; + wdatB <= x"11_22_33_f0"; + pulseB; + assert rdatB = x"11_22_33_f1" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/synth109/testsuite.sh b/testsuite/synth/synth109/testsuite.sh new file mode 100755 index 000000000..0b9a92e5d --- /dev/null +++ b/testsuite/synth/synth109/testsuite.sh @@ -0,0 +1,13 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS="-fsynopsys" +synth_tb ram1 +synth_tb ram2 +#synth_tb ram4 + +synth_analyze ram9 +synth asymmetric_ram_2a.vhd -e > syn_asymmetric_ram_2a.vhdl + +echo "Test successful" |