diff options
| -rw-r--r-- | testsuite/synth/issue1077/ent.vhdl | 30 | ||||
| -rwxr-xr-x | testsuite/synth/issue1077/testsuite.sh | 12 |
2 files changed, 42 insertions, 0 deletions
diff --git a/testsuite/synth/issue1077/ent.vhdl b/testsuite/synth/issue1077/ent.vhdl new file mode 100644 index 000000000..d1e6303e6 --- /dev/null +++ b/testsuite/synth/issue1077/ent.vhdl @@ -0,0 +1,30 @@ +library ieee; +use ieee.std_logic_1164.all, + ieee.numeric_std.all; + +entity ent is + port ( + clk : in std_logic; + i : in std_logic_vector(7 downto 0); + + amount : in integer range 0 to 7; + + const_half : out signed(7 downto 0); + async_ror : out std_logic_vector(7 downto 0); + clocked_left : out unsigned(7 downto 0) + ); +end; + +architecture a of ent is + constant ONE : unsigned(3 downto 0) := x"4" srl 2; +begin + const_half <= signed(i) sra to_integer(ONE); + async_ror <= i ror amount; + + process(clk) + begin + if rising_edge(clk) then + clocked_left <= unsigned(i) sll amount; + end if; + end process; +end; diff --git a/testsuite/synth/issue1077/testsuite.sh b/testsuite/synth/issue1077/testsuite.sh new file mode 100755 index 000000000..b6f55d91d --- /dev/null +++ b/testsuite/synth/issue1077/testsuite.sh @@ -0,0 +1,12 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +for t in ent; do + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl + clean +done + +echo "Test successful" |