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-rw-r--r--testsuite/synth/issue1041/ent.vhdl38
-rwxr-xr-xtestsuite/synth/issue1041/testsuite.sh13
2 files changed, 51 insertions, 0 deletions
diff --git a/testsuite/synth/issue1041/ent.vhdl b/testsuite/synth/issue1041/ent.vhdl
new file mode 100644
index 000000000..d6b40a1f8
--- /dev/null
+++ b/testsuite/synth/issue1041/ent.vhdl
@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent is
+ port (
+ reset : in std_logic;
+ clk : in std_logic
+ );
+end ent;
+
+architecture rtl of ent is
+ function const return natural is
+ begin
+ return 1;
+ end const;
+
+ constant MAX_COUNT : natural := const;
+ signal countdown : natural;
+
+ signal x : std_logic;
+ signal y : std_logic;
+begin
+ x <= '1';
+ y <= '1';
+
+ process(reset, clk)
+ begin
+ if reset then
+ countdown <= MAX_COUNT;
+ elsif rising_edge(clk) then
+ if x then
+ if y then
+ countdown <= MAX_COUNT;
+ end if;
+ end if;
+ end if;
+ end process;
+end rtl;
diff --git a/testsuite/synth/issue1041/testsuite.sh b/testsuite/synth/issue1041/testsuite.sh
new file mode 100755
index 000000000..730cf6d16
--- /dev/null
+++ b/testsuite/synth/issue1041/testsuite.sh
@@ -0,0 +1,13 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+for t in ent; do
+ synth $t.vhdl -e $t > syn_$t.vhdl
+ analyze syn_$t.vhdl
+done
+
+clean
+
+echo "Test successful"