diff options
-rw-r--r-- | testsuite/synth/issue2088/bug.vhdl | 35 | ||||
-rw-r--r-- | testsuite/synth/issue2088/bug2.vhdl | 37 | ||||
-rw-r--r-- | testsuite/synth/issue2088/bug3.vhdl | 36 | ||||
-rwxr-xr-x | testsuite/synth/issue2088/testsuite.sh | 9 |
4 files changed, 117 insertions, 0 deletions
diff --git a/testsuite/synth/issue2088/bug.vhdl b/testsuite/synth/issue2088/bug.vhdl new file mode 100644 index 000000000..c71baf120 --- /dev/null +++ b/testsuite/synth/issue2088/bug.vhdl @@ -0,0 +1,35 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity bug is +port( + clk : in std_ulogic +); +end entity; + +architecture rtl of bug is + + type table_t is array (natural range<>, natural range<>) of integer; + + function fun1(table : table_t) return integer is + constant len : natural := table'length(2); + begin + return len; + end function; + + function fun2(table : table_t) return integer is + variable tmp : natural; + begin + tmp := 0; + for i in table'range(2) loop + tmp := tmp+1; + end loop; + return tmp; + end function; + + constant table : table_t(0 to 15, 0 to 31) := (others => (others => 0)); + constant l1 : natural := fun1(table); + constant l2 : natural := fun2(table); +begin + +end architecture; diff --git a/testsuite/synth/issue2088/bug2.vhdl b/testsuite/synth/issue2088/bug2.vhdl new file mode 100644 index 000000000..029811162 --- /dev/null +++ b/testsuite/synth/issue2088/bug2.vhdl @@ -0,0 +1,37 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity bug2 is +port( + clk : in std_ulogic +); +end entity; + +architecture rtl of bug2 is + + type table_t is array (natural range<>, natural range<>) of integer; + + function fun1(table : table_t) return integer is + constant len : natural := table'length(2); + begin + return len; + end function; + + function fun2(table : table_t) return integer is + variable tmp : natural; + begin + tmp := 0; + for i in table'range(2) loop + tmp := tmp+1; + end loop; + return tmp; + end function; + + constant table : table_t(0 to 15, 0 to 31) := (others => (others => 0)); + constant l1 : natural := fun1(table); + constant l2 : natural := fun2(table); +begin + + assert table'left(1) = 0; + assert table'right(2) = 31; +end architecture; diff --git a/testsuite/synth/issue2088/bug3.vhdl b/testsuite/synth/issue2088/bug3.vhdl new file mode 100644 index 000000000..cca04c866 --- /dev/null +++ b/testsuite/synth/issue2088/bug3.vhdl @@ -0,0 +1,36 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity bug2 is +port( + clk : in std_ulogic +); +end entity; + +architecture rtl of bug2 is + + type table_t is array (natural range<>, natural range<>) of integer; + + function fun1(table : table_t) return integer is + constant len : natural := table'length(2); + begin + return len; + end function; + + function fun2(table : table_t) return integer is + variable tmp : natural; + begin + tmp := 0; + for i in table'range(2) loop + tmp := tmp+1; + end loop; + return tmp; + end function; + + constant table : table_t(0 to 15, 0 to 31) := (others => (others => 0)); + constant l1 : natural := fun1(table); + constant l2 : natural := fun2(table); +begin + + assert table'right(2) = 15; -- Wrong +end architecture; diff --git a/testsuite/synth/issue2088/testsuite.sh b/testsuite/synth/issue2088/testsuite.sh new file mode 100755 index 000000000..76b9779b7 --- /dev/null +++ b/testsuite/synth/issue2088/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_only bug +synth_only bug2 +synth_failure bug3.vhdl -e + +echo "Test successful" |