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-rw-r--r--testsuite/gna/bug0117/repro12.vhdl24
-rwxr-xr-xtestsuite/gna/bug0117/testsuite.sh2
2 files changed, 25 insertions, 1 deletions
diff --git a/testsuite/gna/bug0117/repro12.vhdl b/testsuite/gna/bug0117/repro12.vhdl
new file mode 100644
index 000000000..d5ab41098
--- /dev/null
+++ b/testsuite/gna/bug0117/repro12.vhdl
@@ -0,0 +1,24 @@
+entity repro12 is
+end;
+
+architecture behav of repro12 is
+ type my_arr is array (natural range <>) of bit_vector;
+
+ procedure assign (v : inout my_arr; d : my_arr) is
+ begin
+ v (d'length - 1 downto 0) := d;
+ end assign;
+begin
+ process
+ variable v1 : my_arr (2 downto 0)(3 downto 0);
+ variable v0 : my_arr (1 downto 0)(3 downto 0);
+ begin
+ v0 := (x"1", x"2");
+ v1 := (x"5", x"4", x"3");
+ assign (v1, v0);
+ assert v1(2) = x"5";
+ assert v1(1) = x"1";
+ assert v1(0) = x"2";
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/gna/bug0117/testsuite.sh b/testsuite/gna/bug0117/testsuite.sh
index 0b9fde62d..bcf7bfba2 100755
--- a/testsuite/gna/bug0117/testsuite.sh
+++ b/testsuite/gna/bug0117/testsuite.sh
@@ -3,7 +3,7 @@
. ../../testenv.sh
export GHDL_STD_FLAGS=--std=08
-for i in repro1 repro4 repro5 repro6 repro7 repro8; do
+for i in repro1 repro4 repro5 repro6 repro7 repro8 repro12; do
analyze $i.vhdl
elab_simulate $i
done