diff options
| -rw-r--r-- | src/synth/synth-expr.adb | 3 | ||||
| -rw-r--r-- | src/synth/synth-oper.adb | 2 | ||||
| -rw-r--r-- | src/synth/synth-values.adb | 1 | ||||
| -rw-r--r-- | src/synth/synth-values.ads | 5 | 
4 files changed, 1 insertions, 10 deletions
| diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index f0ba02b40..d5a309291 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -584,7 +584,6 @@ package body Synth.Expr is           Len := 0;        end if;        return (Dir => Rng.Dir, -              Wlen => Width (Clog2 (Uns64 (Len))),                Wbounds => W,                Left => Int32 (Rng.Left), Right => Int32 (Rng.Right),                Len => Uns32 (Len)); @@ -1237,7 +1236,6 @@ package body Synth.Expr is                 when Iir_To =>                    Len := Uns32 (R - L + 1);                    Res_Bnd := (Dir => Iir_To, -                              Wlen => Len,                                Wbounds => Pfx_Bnd.Wbounds,                                Len => Len,                                Left => Int32 (L), @@ -1246,7 +1244,6 @@ package body Synth.Expr is                 when Iir_Downto =>                    Len := Uns32 (L - R + 1);                    Res_Bnd := (Dir => Iir_Downto, -                              Wlen => Len,                                Wbounds => Pfx_Bnd.Wbounds,                                Len => Len,                                Left => Int32 (L), diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 13afb0ea8..92508f36d 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -21,7 +21,6 @@  with Ada.Unchecked_Conversion;  with Types; use Types;  with Types_Utils; use Types_Utils; -with Mutils; use Mutils;  with Vhdl.Ieee.Std_Logic_1164; use Vhdl.Ieee.Std_Logic_1164;  with Vhdl.Std_Package;  with Vhdl.Errors; use Vhdl.Errors; @@ -160,7 +159,6 @@ package body Synth.Oper is                Right => 0,                Dir => Index_Bounds.Dir,                Wbounds => W, -              Wlen => Width (Clog2 (Uns64 (Len))),                Len => Uns32 (Len));        if Len = 0 then diff --git a/src/synth/synth-values.adb b/src/synth/synth-values.adb index 22bbd4fba..30695afa2 100644 --- a/src/synth/synth-values.adb +++ b/src/synth/synth-values.adb @@ -231,7 +231,6 @@ package body Synth.Values is        W : constant Width := Uns32 (Clog2 (Uns64 (Len)));     begin        return Create_Vector_Type ((Dir => Iir_Downto, -                                  Wlen => W,                                    Wbounds => W,                                    Left => Int32 (Len) - 1,                                    Right => 0, diff --git a/src/synth/synth-values.ads b/src/synth/synth-values.ads index 28661d41a..5fc406e9e 100644 --- a/src/synth/synth-values.ads +++ b/src/synth/synth-values.ads @@ -52,13 +52,10 @@ package Synth.Values is        Right : Int32;        Len : Width; -      --  Width of length.  This is the number of address bits. -      Wlen : Width; -        --  Width of bounds.  This is the precision used to compute the        --  address.        --  If bounds are 1 to 128 (so left = 1, dir = to, right = 128), -      --  Wlen = 7 and Wbounds = 8. +      --  Wbounds = 8.        Wbounds : Width;     end record; | 
