diff options
| -rw-r--r-- | python/libghdl/thin/std_names.py | 343 | ||||
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 4 | ||||
| -rw-r--r-- | src/std_names.adb | 1 | ||||
| -rw-r--r-- | src/std_names.ads | 7 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_arith.adb | 169 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_arith.ads | 22 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 8 | ||||
| -rw-r--r-- | src/vhdl/vhdl-post_sems.adb | 3 |
8 files changed, 382 insertions, 175 deletions
diff --git a/python/libghdl/thin/std_names.py b/python/libghdl/thin/std_names.py index 5ff5879d9..c2ddef117 100644 --- a/python/libghdl/thin/std_names.py +++ b/python/libghdl/thin/std_names.py @@ -595,174 +595,175 @@ class Name: Rotate_Left = 809 Rotate_Right = 810 To_Bitvector = 811 - Math_Real = 812 - Ceil = 813 - Log2 = 814 - Last_Ieee = 814 - First_Directive = 815 - Define = 815 - Endif = 816 - Ifdef = 817 - Ifndef = 818 - Include = 819 - Timescale = 820 - Undef = 821 - Protect = 822 - Begin_Protected = 823 - End_Protected = 824 - Key_Block = 825 - Data_Block = 826 - Line = 827 - Celldefine = 828 - Endcelldefine = 829 - Default_Nettype = 830 - Resetall = 831 - Last_Directive = 831 - First_Systask = 832 - Bits = 832 - D_Root = 833 - D_Unit = 834 - Last_Systask = 834 - First_SV_Method = 835 - Size = 835 - Insert = 836 - Delete = 837 - Pop_Front = 838 - Pop_Back = 839 - Push_Front = 840 - Push_Back = 841 - Name = 842 - Len = 843 - Substr = 844 - Exists = 845 - Atoi = 846 - Itoa = 847 - Find = 848 - Find_Index = 849 - Find_First = 850 - Find_First_Index = 851 - Find_Last = 852 - Find_Last_Index = 853 - Num = 854 - Randomize = 855 - Pre_Randomize = 856 - Post_Randomize = 857 - Srandom = 858 - Get_Randstate = 859 - Set_Randstate = 860 - Seed = 861 - State = 862 - Last_SV_Method = 862 - First_BSV = 863 - uAction = 863 - uActionValue = 864 - BVI = 865 - uC = 866 - uCF = 867 - uE = 868 - uSB = 869 - uSBR = 870 - Action = 871 - Endaction = 872 - Actionvalue = 873 - Endactionvalue = 874 - Ancestor = 875 - Clocked_By = 876 - Default_Clock = 877 - Default_Reset = 878 - Dependencies = 879 - Deriving = 880 - Determines = 881 - Enable = 882 - Ifc_Inout = 883 - Input_Clock = 884 - Input_Reset = 885 - Instance = 886 - Endinstance = 887 - Let = 888 - Match = 889 - Method = 890 - Endmethod = 891 - Numeric = 892 - Output_Clock = 893 - Output_Reset = 894 - Par = 895 - Endpar = 896 - Path = 897 - Provisos = 898 - Ready = 899 - Reset_By = 900 - Rule = 901 - Endrule = 902 - Rules = 903 - Endrules = 904 - Same_Family = 905 - Schedule = 906 - Seq = 907 - Endseq = 908 - Typeclass = 909 - Endtypeclass = 910 - Valueof = 911 - uValueof = 912 - Last_BSV = 912 - First_Comment = 913 - Psl = 913 - Pragma = 914 - Last_Comment = 914 - First_PSL = 915 - A = 915 - Af = 916 - Ag = 917 - Ax = 918 - Abort = 919 - Assume_Guarantee = 920 - Before = 921 - Clock = 922 - E = 923 - Ef = 924 - Eg = 925 - Ex = 926 - Endpoint = 927 - Eventually = 928 - Fairness = 929 - Fell = 930 - Forall = 931 - G = 932 - Inf = 933 - Inherit = 934 - Never = 935 - Next_A = 936 - Next_E = 937 - Next_Event = 938 - Next_Event_A = 939 - Next_Event_E = 940 - Prev = 941 - Rose = 942 - Strong = 943 - W = 944 - Whilenot = 945 - Within = 946 - X = 947 - Last_PSL = 947 - First_Edif = 948 - Celltype = 958 - View = 959 - Viewtype = 960 - Direction = 961 - Contents = 962 - Net = 963 - Viewref = 964 - Cellref = 965 - Libraryref = 966 - Portinstance = 967 - Joined = 968 - Portref = 969 - Instanceref = 970 - Design = 971 - Designator = 972 - Owner = 973 - Member = 974 - Number = 975 - Rename = 976 - Userdata = 977 - Last_Edif = 977 + Conv_Unsigned = 812 + Math_Real = 813 + Ceil = 814 + Log2 = 815 + Last_Ieee = 815 + First_Directive = 816 + Define = 816 + Endif = 817 + Ifdef = 818 + Ifndef = 819 + Include = 820 + Timescale = 821 + Undef = 822 + Protect = 823 + Begin_Protected = 824 + End_Protected = 825 + Key_Block = 826 + Data_Block = 827 + Line = 828 + Celldefine = 829 + Endcelldefine = 830 + Default_Nettype = 831 + Resetall = 832 + Last_Directive = 832 + First_Systask = 833 + Bits = 833 + D_Root = 834 + D_Unit = 835 + Last_Systask = 835 + First_SV_Method = 836 + Size = 836 + Insert = 837 + Delete = 838 + Pop_Front = 839 + Pop_Back = 840 + Push_Front = 841 + Push_Back = 842 + Name = 843 + Len = 844 + Substr = 845 + Exists = 846 + Atoi = 847 + Itoa = 848 + Find = 849 + Find_Index = 850 + Find_First = 851 + Find_First_Index = 852 + Find_Last = 853 + Find_Last_Index = 854 + Num = 855 + Randomize = 856 + Pre_Randomize = 857 + Post_Randomize = 858 + Srandom = 859 + Get_Randstate = 860 + Set_Randstate = 861 + Seed = 862 + State = 863 + Last_SV_Method = 863 + First_BSV = 864 + uAction = 864 + uActionValue = 865 + BVI = 866 + uC = 867 + uCF = 868 + uE = 869 + uSB = 870 + uSBR = 871 + Action = 872 + Endaction = 873 + Actionvalue = 874 + Endactionvalue = 875 + Ancestor = 876 + Clocked_By = 877 + Default_Clock = 878 + Default_Reset = 879 + Dependencies = 880 + Deriving = 881 + Determines = 882 + Enable = 883 + Ifc_Inout = 884 + Input_Clock = 885 + Input_Reset = 886 + Instance = 887 + Endinstance = 888 + Let = 889 + Match = 890 + Method = 891 + Endmethod = 892 + Numeric = 893 + Output_Clock = 894 + Output_Reset = 895 + Par = 896 + Endpar = 897 + Path = 898 + Provisos = 899 + Ready = 900 + Reset_By = 901 + Rule = 902 + Endrule = 903 + Rules = 904 + Endrules = 905 + Same_Family = 906 + Schedule = 907 + Seq = 908 + Endseq = 909 + Typeclass = 910 + Endtypeclass = 911 + Valueof = 912 + uValueof = 913 + Last_BSV = 913 + First_Comment = 914 + Psl = 914 + Pragma = 915 + Last_Comment = 915 + First_PSL = 916 + A = 916 + Af = 917 + Ag = 918 + Ax = 919 + Abort = 920 + Assume_Guarantee = 921 + Before = 922 + Clock = 923 + E = 924 + Ef = 925 + Eg = 926 + Ex = 927 + Endpoint = 928 + Eventually = 929 + Fairness = 930 + Fell = 931 + Forall = 932 + G = 933 + Inf = 934 + Inherit = 935 + Never = 936 + Next_A = 937 + Next_E = 938 + Next_Event = 939 + Next_Event_A = 940 + Next_Event_E = 941 + Prev = 942 + Rose = 943 + Strong = 944 + W = 945 + Whilenot = 946 + Within = 947 + X = 948 + Last_PSL = 948 + First_Edif = 949 + Celltype = 959 + View = 960 + Viewtype = 961 + Direction = 962 + Contents = 963 + Net = 964 + Viewref = 965 + Cellref = 966 + Libraryref = 967 + Portinstance = 968 + Joined = 969 + Portref = 970 + Instanceref = 971 + Design = 972 + Designator = 973 + Owner = 974 + Member = 975 + Number = 976 + Rename = 977 + Userdata = 978 + Last_Edif = 978 diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 3d3323bc6..08feba5fc 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1194,6 +1194,10 @@ class Iir_Predefined: Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 315 Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 316 Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 317 + Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 318 + Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 319 + Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 320 + Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 321 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location diff --git a/src/std_names.adb b/src/std_names.adb index 3338c805d..f1042a7d9 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -647,6 +647,7 @@ package body Std_Names is Def ("rotate_left", Name_Rotate_Left); Def ("rotate_right", Name_Rotate_Right); Def ("to_bitvector", Name_To_Bitvector); + Def ("conv_unsigned", Name_Conv_Unsigned); Def ("math_real", Name_Math_Real); Def ("ceil", Name_Ceil); Def ("log2", Name_Log2); diff --git a/src/std_names.ads b/src/std_names.ads index ff489c8bf..81a878ee4 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -728,9 +728,10 @@ package Std_Names is Name_Rotate_Left : constant Name_Id := Name_First_Ieee + 026; Name_Rotate_Right : constant Name_Id := Name_First_Ieee + 027; Name_To_Bitvector : constant Name_Id := Name_First_Ieee + 028; - Name_Math_Real : constant Name_Id := Name_First_Ieee + 029; - Name_Ceil : constant Name_Id := Name_First_Ieee + 030; - Name_Log2 : constant Name_Id := Name_First_Ieee + 031; + Name_Conv_Unsigned : constant Name_Id := Name_First_Ieee + 029; + Name_Math_Real : constant Name_Id := Name_First_Ieee + 030; + Name_Ceil : constant Name_Id := Name_First_Ieee + 031; + Name_Log2 : constant Name_Id := Name_First_Ieee + 032; Name_Last_Ieee : constant Name_Id := Name_Log2; -- Verilog Directives. diff --git a/src/vhdl/vhdl-ieee-std_logic_arith.adb b/src/vhdl/vhdl-ieee-std_logic_arith.adb new file mode 100644 index 000000000..ab6ba9646 --- /dev/null +++ b/src/vhdl/vhdl-ieee-std_logic_arith.adb @@ -0,0 +1,169 @@ +-- Nodes recognizer for ieee.std_logic_arith. +-- Copyright (C) 2019 Tristan Gingold +-- +-- GHDL is free software; you can redistribute it and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation; either version 2, or (at your option) any later +-- version. +-- +-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY +-- WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with GHDL; see the file COPYING. If not, write to the Free +-- Software Foundation, 59 Temple Place - Suite 330, Boston, MA +-- 02111-1307, USA. + +with Types; use Types; +with Vhdl.Std_Package; +with Std_Names; use Std_Names; +with Vhdl.Errors; use Vhdl.Errors; +with Vhdl.Ieee.Std_Logic_1164; + +package body Vhdl.Ieee.Std_Logic_Arith is + -- Unsigned and signed type definition. + Unsigned_Type : Iir := Null_Iir; + Signed_Type : Iir := Null_Iir; + + type Arg_Kind is (Type_Signed, Type_Unsigned, Type_Int, + Type_Log, Type_Slv); + + Error : exception; + + procedure Extract_Declarations (Pkg : Iir_Package_Declaration) + is + procedure Classify_Arg (Arg : Iir; Kind : out Arg_Kind) + is + Arg_Type : constant Iir := Get_Type (Arg); + begin + if Arg_Type = Signed_Type then + Kind := Type_Signed; + elsif Arg_Type = Unsigned_Type then + Kind := Type_Unsigned; + elsif Arg_Type = Vhdl.Std_Package.Integer_Subtype_Definition then + Kind := Type_Int; + elsif Arg_Type = Ieee.Std_Logic_1164.Std_Ulogic_Type then + Kind := Type_Log; + elsif Arg_Type = Ieee.Std_Logic_1164.Std_Logic_Vector_Type then + Kind := Type_Slv; + else + raise Error; + end if; + end Classify_Arg; + + Decl : Iir; + Type_Def : Iir; + + Arg1, Arg2 : Iir; + Arg1_Kind, Arg2_Kind : Arg_Kind; + + function Handle_Conv_Unsigned return Iir_Predefined_Functions is + begin + if Arg2_Kind /= Type_Int then + raise Error; + end if; + case Arg1_Kind is + when Type_Int => + return Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int; + when Type_Unsigned => + return Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Uns; + when Type_Signed => + return Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn; + when Type_Log => + return Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Log; + when others => + raise Error; + end case; + end Handle_Conv_Unsigned; + + Def : Iir_Predefined_Functions; + begin + Decl := Get_Declaration_Chain (Pkg); + + -- The first declaration should be type Unsigned. + if not (Decl /= Null_Iir + and then Get_Kind (Decl) = Iir_Kind_Type_Declaration + and then Get_Identifier (Decl) = Name_Unsigned) + then + raise Error; + end if; + + Type_Def := Get_Type_Definition (Decl); + if Get_Kind (Type_Def) /= Iir_Kind_Array_Type_Definition then + raise Error; + end if; + Unsigned_Type := Type_Def; + + -- The second declaration should be type Signed. + Decl := Get_Chain (Decl); + Decl := Skip_Implicit (Decl); + if not (Decl /= Null_Iir + and then Get_Kind (Decl) = Iir_Kind_Type_Declaration + and then Get_Identifier (Decl) = Name_Signed) + then + raise Error; + end if; + + Type_Def := Get_Type_Definition (Decl); + if Get_Kind (Type_Def) /= Iir_Kind_Array_Type_Definition then + raise Error; + end if; + Signed_Type := Type_Def; + + -- Skip subtypes + Decl := Get_Chain (Decl); + Decl := Skip_Implicit (Decl); + while Is_Valid (Decl) loop + exit when Get_Kind (Decl) /= Iir_Kind_Subtype_Declaration; + Decl := Get_Chain (Decl); + end loop; + + -- Handle functions. + while Is_Valid (Decl) loop + Def := Iir_Predefined_None; + + case Get_Kind (Decl) is + when Iir_Kind_Function_Declaration => + Arg1 := Get_Interface_Declaration_Chain (Decl); + if Is_Null (Arg1) then + raise Error; + end if; + + Classify_Arg (Arg1, Arg1_Kind); + Arg2 := Get_Chain (Arg1); + if Is_Valid (Arg2) then + -- Dyadic function. + Classify_Arg (Arg2, Arg2_Kind); + + case Get_Identifier (Decl) is + when Name_Conv_Unsigned => + Def := Handle_Conv_Unsigned; + when others => + null; + end case; + else + -- Monadic function. + case Get_Identifier (Decl) is + when others => + null; + end case; + end if; + + when Iir_Kind_Non_Object_Alias_Declaration + | Iir_Kind_Procedure_Declaration => + null; + + when others => + raise Error; + end case; + Set_Implicit_Definition (Decl, Def); + + Decl := Get_Chain (Decl); + end loop; + exception + when Error => + Error_Msg_Sem (+Pkg, "package ieee.std_logic_arith is ill-formed"); + end Extract_Declarations; +end Vhdl.Ieee.Std_Logic_Arith; diff --git a/src/vhdl/vhdl-ieee-std_logic_arith.ads b/src/vhdl/vhdl-ieee-std_logic_arith.ads new file mode 100644 index 000000000..a6007aa22 --- /dev/null +++ b/src/vhdl/vhdl-ieee-std_logic_arith.ads @@ -0,0 +1,22 @@ +-- Nodes recognizer for ieee.std_logic_arith +-- Copyright (C) 2019 Tristan Gingold +-- +-- GHDL is free software; you can redistribute it and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation; either version 2, or (at your option) any later +-- version. +-- +-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY +-- WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with GHDL; see the file COPYING. If not, write to the Free +-- Software Foundation, 59 Temple Place - Suite 330, Boston, MA +-- 02111-1307, USA. + +package Vhdl.Ieee.Std_Logic_Arith is + -- Extract declarations from PKG . + procedure Extract_Declarations (Pkg : Iir_Package_Declaration); +end Vhdl.Ieee.Std_Logic_Arith; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 552325c07..840f0bb70 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5085,7 +5085,13 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Slv_Int, - Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Int_Slv + Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Int_Slv, + + -- std_logic_arith (synopsys extention). + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Log ); -- Return TRUE iff FUNC is a short-cut predefined function. diff --git a/src/vhdl/vhdl-post_sems.adb b/src/vhdl/vhdl-post_sems.adb index 28f0c54d7..e5805ea59 100644 --- a/src/vhdl/vhdl-post_sems.adb +++ b/src/vhdl/vhdl-post_sems.adb @@ -23,6 +23,7 @@ with Vhdl.Ieee.Vital_Timing; with Vhdl.Ieee.Numeric; with Vhdl.Ieee.Math_Real; with Vhdl.Ieee.Std_Logic_Unsigned; +with Vhdl.Ieee.Std_Logic_Arith; with Flags; use Flags; package body Vhdl.Post_Sems is @@ -63,6 +64,8 @@ package body Vhdl.Post_Sems is Vhdl.Ieee.Math_Real.Extract_Declarations (Lib_Unit); when Name_Std_Logic_Unsigned => Vhdl.Ieee.Std_Logic_Unsigned.Extract_Declarations (Lib_Unit); + when Name_Std_Logic_Arith => + Vhdl.Ieee.Std_Logic_Arith.Extract_Declarations (Lib_Unit); when others => null; end case; |