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-rw-r--r--doc/using/InvokingGHDL.rst68
-rw-r--r--libraries/std/textio_body.vhdl2
-rw-r--r--src/ortho/llvm-nodebug/ortho_llvm.adb2
-rw-r--r--src/ortho/llvm/ortho_llvm.adb2
-rw-r--r--src/ortho/llvm4-nodebug/ortho_llvm.adb2
-rw-r--r--src/vhdl/iirs.ads4
-rw-r--r--src/vhdl/scanner.adb2
-rw-r--r--src/vhdl/sem.adb2
-rw-r--r--src/vhdl/sem_expr.adb6
-rw-r--r--src/vhdl/sem_names.ads2
-rw-r--r--src/vhdl/sem_specs.adb2
-rw-r--r--src/vhdl/simulate/simul-elaboration.adb11
-rw-r--r--src/vhdl/translate/trans-chap12.adb2
-rw-r--r--src/vhdl/translate/trans-chap7.adb2
14 files changed, 70 insertions, 39 deletions
diff --git a/doc/using/InvokingGHDL.rst b/doc/using/InvokingGHDL.rst
index e64c695c6..758b2529b 100644
--- a/doc/using/InvokingGHDL.rst
+++ b/doc/using/InvokingGHDL.rst
@@ -184,7 +184,7 @@ This is not perfect, since the default architecture (the most recently analyzed
.. index:: cmd generate makefile
Generate Makefile [``--gen-makefile``]
-------------------------------------------
+--------------------------------------
.. option:: --gen-makefile <[options] primary [secondary]>
@@ -193,7 +193,7 @@ This command works like the make command (see :option:`-m`), but only a makefile
.. index:: --gen-depends command
Generate dependency file command [``--gen-depends``]
--------------------------
+----------------------------------------------------
.. option:: --gen-depends <[options] primary [secondary]>
@@ -216,7 +216,7 @@ Options
.. index:: WORK library
-.. option:: --work<=NAME>
+.. option:: --work=<NAME>
Specify the name of the ``WORK`` library. Analyzed units are always placed in the library logically named ``WORK``. With this option, you can set its name. By default, the name is ``work``.
@@ -224,17 +224,17 @@ Options
`VHDL` rules forbid you from adding units to the ``std`` library. Furthermore, you should not put units in the ``ieee`` library.
-.. option:: --workdir<=DIR>
+.. option:: --workdir=<DIR>
Specify the directory where the ``WORK`` library is located. When this option is not present, the ``WORK`` library is in the current directory. The object files created by the compiler are always placed in the same directory as the ``WORK`` library.
Use option :option:`-P` to specify where libraries other than ``WORK`` are placed.
-.. option:: --std<=STD>
+.. option:: --std=<STD>
Specify the standard to use. By default, the standard is ``93c``, which means VHDL-93 accepting VHDL-87 syntax. For details on ``STD`` values see section :ref:`VHDL_standards`.
-.. option:: --ieee<=VER>
+.. option:: --ieee=<VER>
.. index:: ieee library
.. index:: synopsys library
@@ -344,9 +344,9 @@ Some constructions are not erroneous but dubious. Warnings are diagnostic messag
.. HINT::
You could disable a warning by using the ``--warn-no-XXX`` or ``-Wno-XXX`` instead of ``--warn-XXX`` or ``-WXXX``.
-.. option:: --warn-reserved
+.. option:: --warn-library
- Emit a warning if an identifier is a reserved word in a later VHDL standard.
+ Warns if a design unit replaces another design unit with the same name.
.. option:: --warn-default-binding
@@ -358,9 +358,17 @@ Some constructions are not erroneous but dubious. Warnings are diagnostic messag
However, warnings are still emitted if a component instantiation is inside a generate statement. As a consequence, if you use the conditional generate statement to select a component according to the implementation, you will certainly get warnings.
-.. option:: --warn-library
+.. option:: --warn-reserved
- Warns if a design unit replaces another design unit with the same name.
+ Emit a warning if an identifier is a reserved word in a later VHDL standard.
+
+.. option:: --warn-nested-comment
+
+ Emit a warning if a ``/*`` appears within a block comment (vhdl 2008).
+
+.. option:: --warn-parenthesis
+
+ Emit a warning in case of weird use of parentheses.
.. option:: --warn-vital-generic
@@ -381,26 +389,42 @@ Some constructions are not erroneous but dubious. Warnings are diagnostic messag
Emit a warning if an all or others specification does not apply.
+.. option:: --warn-runtime-error
+
+ Emit a warning in case of runtime error that is detected during
+ analysis.
+
+.. option:: --warn-shared
+
+ Emit a warning when a shared variable is declared and its type it
+ not a protected type.
+
+.. option:: --warn-hide
+
+ Emit a warning when a declaration hides a previous hide.
+
.. option:: --warn-unused
Emit a warning when a subprogram is never used.
-.. option:: --warn-error
+.. option:: --warn-others
- When this option is set, warnings are considered as errors.
+ Emit a warning is an `others` choice is not required because all the
+ choices have been explicitly covered.
-.. option:: --warn-nested-comment
+.. option:: --warn-pure
- Emit a warning if a ``/*`` appears within a block comment (vhdl 2008).
+ Emit a warning when a pure rules is violated (like declaring a pure
+ function with access parameters).
-.. option:: --warn-parenthesis
+.. option:: --warn-static
- Emit a warning in case of weird use of parentheses.
+ Emit a warning when a non-static expression is used at a place where
+ the standard requires a static expression.
-.. option:: --warn-runtime-error
+.. option:: --warn-error
- Emit a warning in case of runtime error that is detected during
- analysis.
+ When this option is set, warnings are considered as errors.
Diagnostics Control
@@ -416,6 +440,12 @@ Diagnostics Control
Control whether the warning option is displayed at the end of warning messages, so that the user can easily know how to disable it.
+.. option:: -fcaret-diagnostics
+.. option:: -fno-caret-diagnostics
+
+ Control whether the source line of the error is displayed with a
+ caret indicating the column of the error.
+
Library commands
================
diff --git a/libraries/std/textio_body.vhdl b/libraries/std/textio_body.vhdl
index 36a11fc23..83a9a00da 100644
--- a/libraries/std/textio_body.vhdl
+++ b/libraries/std/textio_body.vhdl
@@ -27,7 +27,7 @@ package body textio is
-- value 0 for the FIELD parameter has the effect of causing the string
-- value to be contained in a field of exactly the right widteh (i.e., no
-- additional leading or tailing spaces). Parameter JUSTIFIED specified
- -- wether the string value is to be right- or left-justified within the
+ -- whether the string value is to be right- or left-justified within the
-- field; the default is right-justified. If the FIELD parameter describes
-- a field width larger than the number of characters in the string value,
-- space characters are used to fill the remaining characters in the field.
diff --git a/src/ortho/llvm-nodebug/ortho_llvm.adb b/src/ortho/llvm-nodebug/ortho_llvm.adb
index 9edc264a7..7eb7277c6 100644
--- a/src/ortho/llvm-nodebug/ortho_llvm.adb
+++ b/src/ortho/llvm-nodebug/ortho_llvm.adb
@@ -27,7 +27,7 @@ package body Ortho_LLVM is
-- The current function node (needed for return type).
Cur_Func_Decl : O_Dnode;
- -- Wether the code is currently unreachable. LLVM doesn't accept basic
+ -- Whether the code is currently unreachable. LLVM doesn't accept basic
-- blocks that cannot be reached (using trivial rules). So we need to
-- discard instructions after a return, a next or an exit statement.
Unreach : Boolean;
diff --git a/src/ortho/llvm/ortho_llvm.adb b/src/ortho/llvm/ortho_llvm.adb
index 7e3ee626c..d5e172532 100644
--- a/src/ortho/llvm/ortho_llvm.adb
+++ b/src/ortho/llvm/ortho_llvm.adb
@@ -28,7 +28,7 @@ package body Ortho_LLVM is
-- The current function node (needed for return type).
Cur_Func_Decl : O_Dnode;
- -- Wether the code is currently unreachable. LLVM doesn't accept basic
+ -- Whether the code is currently unreachable. LLVM doesn't accept basic
-- blocks that cannot be reached (using trivial rules). So we need to
-- discard instructions after a return, a next or an exit statement.
Unreach : Boolean;
diff --git a/src/ortho/llvm4-nodebug/ortho_llvm.adb b/src/ortho/llvm4-nodebug/ortho_llvm.adb
index 15090e216..4e02a908a 100644
--- a/src/ortho/llvm4-nodebug/ortho_llvm.adb
+++ b/src/ortho/llvm4-nodebug/ortho_llvm.adb
@@ -27,7 +27,7 @@ package body Ortho_LLVM is
-- The current function node (needed for return type).
Cur_Func_Decl : O_Dnode;
- -- Wether the code is currently unreachable. LLVM doesn't accept basic
+ -- Whether the code is currently unreachable. LLVM doesn't accept basic
-- blocks that cannot be reached (using trivial rules). So we need to
-- discard instructions after a return, a next or an exit statement.
Unreach : Boolean;
diff --git a/src/vhdl/iirs.ads b/src/vhdl/iirs.ads
index b2cfeb5fa..47b7cf2cc 100644
--- a/src/vhdl/iirs.ads
+++ b/src/vhdl/iirs.ads
@@ -5930,7 +5930,7 @@ package Iirs is
function Get_Analysis_Checks_List (Unit : Iir) return Iir_List;
procedure Set_Analysis_Checks_List (Unit : Iir; List : Iir_List);
- -- Wether the unit is on disk, parsed or analyzed.
+ -- Whether the unit is on disk, parsed or analyzed.
-- Field: State1 (pos)
function Get_Date_State (Unit : Iir_Design_Unit) return Date_State_Type;
procedure Set_Date_State (Unit : Iir_Design_Unit; State : Date_State_Type);
@@ -6778,7 +6778,7 @@ package Iirs is
function Get_Wait_State (Proc : Iir) return Tri_State_Type;
procedure Set_Wait_State (Proc : Iir; State : Tri_State_Type);
- -- Get/Set wether the subprogram may be called by a sensitized process
+ -- Get/Set whether the subprogram may be called by a sensitized process
-- whose sensitivity list is ALL.
-- FALSE if declared in a package unit and reads a signal that is not
-- one of its interface, or if it calls such a subprogram.
diff --git a/src/vhdl/scanner.adb b/src/vhdl/scanner.adb
index c52714c17..f91357922 100644
--- a/src/vhdl/scanner.adb
+++ b/src/vhdl/scanner.adb
@@ -1670,7 +1670,7 @@ package body Scanner is
-- A comment can appear on any line line of a VHDL
-- description.
-- The presence or absence of comments has no influence on
- -- wether a description is legal or illegal.
+ -- whether a description is legal or illegal.
-- Futhermore, comments do not influence the execution of a
-- simulation module; their sole purpose is the enlightenment
-- of the human reader.
diff --git a/src/vhdl/sem.adb b/src/vhdl/sem.adb
index a19d66179..ec9542f97 100644
--- a/src/vhdl/sem.adb
+++ b/src/vhdl/sem.adb
@@ -630,7 +630,7 @@ package body Sem is
-- LRM93 10.2
-- In addition to the above rules, the scope of any declaration that
- -- includes the end of the declarative part of a given block (wether
+ -- includes the end of the declarative part of a given block (whether
-- it be an external block defined by a design entity or an internal
-- block defined by a block statement) extends into a configuration
-- declaration that configures the given block.
diff --git a/src/vhdl/sem_expr.adb b/src/vhdl/sem_expr.adb
index 11b4e544c..a33212839 100644
--- a/src/vhdl/sem_expr.adb
+++ b/src/vhdl/sem_expr.adb
@@ -2322,9 +2322,9 @@ package body Sem_Expr is
-- LRM 8.8
--
-- If the expression is the name of an object whose subtype is locally
- -- static, wether a scalar type or an array type, then each value of the
- -- subtype must be represented once and only once in the set of choices
- -- of the case statement and no other value is allowed; [...]
+ -- static, whether a scalar type or an array type, then each value of
+ -- the subtype must be represented once and only once in the set of
+ -- choices of the case statement and no other value is allowed; [...]
-- 1. Allocate Arr, fill it and sort
Count_Choices (Info, Choice_Chain);
diff --git a/src/vhdl/sem_names.ads b/src/vhdl/sem_names.ads
index 636dc884e..0e27a8c49 100644
--- a/src/vhdl/sem_names.ads
+++ b/src/vhdl/sem_names.ads
@@ -81,7 +81,7 @@ package Sem_Names is
-- Convert name NAME to an expression (ie, can create function call).
-- A_TYPE is the expected type of the expression.
- -- FIXME: it is unclear wether the result must be an expression or not
+ -- FIXME: it is unclear whether the result must be an expression or not
-- (ie, it *must* have a type, but may be a range).
function Name_To_Expression (Name : Iir; A_Type : Iir) return Iir;
diff --git a/src/vhdl/sem_specs.adb b/src/vhdl/sem_specs.adb
index af5d1c3a4..6e28c5b39 100644
--- a/src/vhdl/sem_specs.adb
+++ b/src/vhdl/sem_specs.adb
@@ -249,7 +249,7 @@ package body Sem_Specs is
-- a given named entity.
-- LRM 5.1
-- Similarly, it is an error if two different attributes with the
- -- same simple name (wether predefined or user-defined) are both
+ -- same simple name (whether predefined or user-defined) are both
-- associated with a given named entity.
Attr_Chain_Parent := Get_Attribute_Value_Chain_Parent (Decl);
El := Get_Attribute_Value_Chain (Attr_Chain_Parent);
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb
index 73a31b287..1e71d7c4f 100644
--- a/src/vhdl/simulate/simul-elaboration.adb
+++ b/src/vhdl/simulate/simul-elaboration.adb
@@ -1493,7 +1493,7 @@ package body Simul.Elaboration is
(Ninstance, Get_Concurrent_Statement_Chain (Block));
-- Elaboration of a block statement may occur under the control of a
-- configuration declaration.
- -- In particular, a block configuration, wether implicit or explicit,
+ -- In particular, a block configuration, whether implicit or explicit,
-- within a configuration declaration may supply a sequence of
-- additionnal implicit configuration specification to be applied
-- during the elaboration of the corresponding block statement.
@@ -1503,10 +1503,11 @@ package body Simul.Elaboration is
-- is elaborated as part of the block declarative part, following all
-- other declarative items in that part.
-- The sequence of implicit configuration specifications supplied by a
- -- block configuration, wether implicit or explicit, consists of each of
- -- the configuration specifications implied by component configurations
- -- occurring immediatly within the block configuration, and in the
- -- order in which the component configurations themselves appear.
+ -- block configuration, whether implicit or explicit, consists of each
+ -- of the configuration specifications implied by component
+ -- configurations occurring immediatly within the block configuration,
+ -- and in the order in which the component configurations themselves
+ -- appear.
-- FIXME.
end Elaborate_Block_Statement;
diff --git a/src/vhdl/translate/trans-chap12.adb b/src/vhdl/translate/trans-chap12.adb
index 9a2d7022e..cad732752 100644
--- a/src/vhdl/translate/trans-chap12.adb
+++ b/src/vhdl/translate/trans-chap12.adb
@@ -708,7 +708,7 @@ package body Trans.Chap12 is
-- Generate code to elaboration body-less package.
--
- -- When a package is analyzed, we don't know wether there is body
+ -- When a package is analyzed, we don't know whether there is body
-- or not. Therefore, we assume there is always a body, and will
-- elaborate the body (which elaborates its spec). If a package
-- has no body, create the body elaboration procedure.
diff --git a/src/vhdl/translate/trans-chap7.adb b/src/vhdl/translate/trans-chap7.adb
index 67ef4bed3..e83cbfe04 100644
--- a/src/vhdl/translate/trans-chap7.adb
+++ b/src/vhdl/translate/trans-chap7.adb
@@ -1215,7 +1215,7 @@ package body Trans.Chap7 is
procedure Walk_Concat (Imp : Iir; L, R : Iir);
-- Call handlers for each leaf of E (an array expression). First
- -- check wether E is also a concatenation.
+ -- check whether E is also a concatenation.
procedure Walk_Arr (E : Iir)
is
Imp : Iir;
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 05:08:15 +0000