diff options
| -rw-r--r-- | testsuite/gna/issue2066/aggregate_bug.vhdl | 18 | ||||
| -rw-r--r-- | testsuite/gna/issue2066/repro1.vhdl | 14 | ||||
| -rwxr-xr-x | testsuite/gna/issue2066/testsuite.sh | 14 |
3 files changed, 46 insertions, 0 deletions
diff --git a/testsuite/gna/issue2066/aggregate_bug.vhdl b/testsuite/gna/issue2066/aggregate_bug.vhdl new file mode 100644 index 000000000..bf7b53510 --- /dev/null +++ b/testsuite/gna/issue2066/aggregate_bug.vhdl @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity aggregate_bug is +end entity aggregate_bug; + +architecture rtl of aggregate_bug is + signal vec : std_logic_vector(7 downto 0); +begin + vec <= (3 downto 0 => "111", others => '0'); -- Associate a 3 bit element to a 4 bit slice + process + begin + wait for 1 ns; + report to_string(vec); + wait for 1 ns; + std.env.finish; + end process; +end architecture rtl; diff --git a/testsuite/gna/issue2066/repro1.vhdl b/testsuite/gna/issue2066/repro1.vhdl new file mode 100644 index 000000000..aa1dfca11 --- /dev/null +++ b/testsuite/gna/issue2066/repro1.vhdl @@ -0,0 +1,14 @@ +entity repro1 is +end; + +architecture rtl of repro1 is + signal vec : bit_vector(7 downto 0); +begin + vec <= (3 downto 0 => "111", others => '0'); -- Associate a 3 bit element to a 4 bit slice + process + begin + wait for 1 ns; + report to_string(vec); + wait; + end process; +end architecture rtl; diff --git a/testsuite/gna/issue2066/testsuite.sh b/testsuite/gna/issue2066/testsuite.sh new file mode 100755 index 000000000..c763a1451 --- /dev/null +++ b/testsuite/gna/issue2066/testsuite.sh @@ -0,0 +1,14 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze repro1.vhdl +elab_simulate_failure repro1 + +analyze aggregate_bug.vhdl +elab_simulate_failure aggregate_bug + +clean + +echo "Test successful" |