diff options
-rw-r--r-- | testsuite/synth/issue662/issue.vhdl | 16 | ||||
-rw-r--r-- | testsuite/synth/issue662/tb_issue.vhdl | 34 | ||||
-rwxr-xr-x | testsuite/synth/issue662/testsuite.sh | 13 |
3 files changed, 63 insertions, 0 deletions
diff --git a/testsuite/synth/issue662/issue.vhdl b/testsuite/synth/issue662/issue.vhdl new file mode 100644 index 000000000..1404b9ecd --- /dev/null +++ b/testsuite/synth/issue662/issue.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity issue is + port (clk, a, b : std_logic); +end entity issue; + + +architecture psl of issue is +begin + -- All is sensitive to rising edge of clk + default clock is rising_edge(clk); + + -- This assertion should fail + stable_1 : assert always (a -> prev(b) = b); +end architecture psl; diff --git a/testsuite/synth/issue662/tb_issue.vhdl b/testsuite/synth/issue662/tb_issue.vhdl new file mode 100644 index 000000000..c679b059f --- /dev/null +++ b/testsuite/synth/issue662/tb_issue.vhdl @@ -0,0 +1,34 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity tb_issue is +end entity tb_issue; + + +architecture psl of tb_issue is + procedure seq (s : string; signal clk : std_logic; signal o : out std_logic) + is + begin + for i in s'range loop + wait until rising_edge(clk); + case s(i) is + when '0' | '_' => o <= '0'; + when '1' | '-' => o <= '1'; + when others => o <= 'X'; + end case; + end loop; + wait; + end seq; + + signal a, b : std_logic := '0'; + signal clk : std_logic := '1'; + +begin + dut: entity work.issue port map (clk, a, b); + + clk <= not clk after 500 ps; + + -- 0123456789012345 + SEQ_A : seq ("__-__-____-__-__", clk, a); + SEQ_B : seq ("____--_______-__", clk, b); +end architecture psl; diff --git a/testsuite/synth/issue662/testsuite.sh b/testsuite/synth/issue662/testsuite.sh new file mode 100755 index 000000000..9f266b29d --- /dev/null +++ b/testsuite/synth/issue662/testsuite.sh @@ -0,0 +1,13 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth_analyze issue +analyze tb_issue.vhdl +elab_simulate_failure tb_issue --stop-time=20ns --asserts=disable-at-0 --assert-level=error +elab_simulate tb_issue --stop-time=10ns --asserts=disable-at-0 --assert-level=error + +clean + +echo "Test successful" |