diff options
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 9 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_stmts.adb | 13 |
2 files changed, 12 insertions, 10 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index d93d13869..e898031bf 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -2245,14 +2245,7 @@ package body Simul.Vhdl_Simul is -- TODO null; when Iir_Kind_Psl_Endpoint_Declaration => - declare - Val : Valtyp; - begin - Val := Create_Value_Memory (Bit_Type, Global_Pool'Access); - Write_Discrete (Val, 0); - -- TODO: create the object/signal during elaboration - Create_Object (Proc.Instance, Proc.Proc, Val); - end; + null; when others => null; end case; diff --git a/src/synth/elab-vhdl_stmts.adb b/src/synth/elab-vhdl_stmts.adb index ebb2380b2..79ef52d26 100644 --- a/src/synth/elab-vhdl_stmts.adb +++ b/src/synth/elab-vhdl_stmts.adb @@ -281,9 +281,18 @@ package body Elab.Vhdl_Stmts is | Iir_Kind_Psl_Assume_Directive | Iir_Kind_Psl_Assert_Directive | Iir_Kind_Psl_Cover_Directive - | Iir_Kind_Psl_Declaration - | Iir_Kind_Psl_Endpoint_Declaration => + | Iir_Kind_Psl_Declaration => null; + when Iir_Kind_Psl_Endpoint_Declaration => + declare + Val : Valtyp; + begin + Val := Create_Value_Memory + (Boolean_Type, Global_Pool'Access); + Write_Discrete (Val, 0); + Create_Object (Syn_Inst, Stmt, Val); + end; + when Iir_Kind_Component_Instantiation_Statement => if Is_Component_Instantiation (Stmt) then Elab_Component_Instantiation_Statement (Syn_Inst, Stmt); |