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-rw-r--r--src/synth/synth-context.adb11
-rw-r--r--src/synth/synth-context.ads2
-rw-r--r--src/synth/synth-decls.adb2
-rw-r--r--src/synth/synth-environment.adb29
-rw-r--r--src/synth/synth-environment.ads60
-rw-r--r--src/synth/synth-insts.adb6
-rw-r--r--src/synth/synth-stmts.adb8
7 files changed, 74 insertions, 44 deletions
diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb
index 46c293c01..382726db4 100644
--- a/src/synth/synth-context.adb
+++ b/src/synth/synth-context.adb
@@ -69,17 +69,6 @@ package body Synth.Context is
return Create_Value_Instance (Packages_Table.Last);
end Create_Value_Instance;
- function Alloc_Wire (Kind : Wire_Kind; Obj : Node) return Wire_Id is
- begin
- Wire_Id_Table.Append ((Kind => Kind,
- Mark_Flag => False,
- Decl => Obj,
- Gate => No_Net,
- Cur_Assign => No_Seq_Assign));
- return Wire_Id_Table.Last;
- end Alloc_Wire;
-
-
function Alloc_Wire (Kind : Wire_Kind; Obj : Iir; Bnd : Value_Bound_Acc)
return Value_Acc
is
diff --git a/src/synth/synth-context.ads b/src/synth/synth-context.ads
index 061d71e32..874962260 100644
--- a/src/synth/synth-context.ads
+++ b/src/synth/synth-context.ads
@@ -74,8 +74,6 @@ package Synth.Context is
return Synth_Instance_Acc;
procedure Free_Instance (Synth_Inst : in out Synth_Instance_Acc);
- function Alloc_Wire (Kind : Wire_Kind; Obj : Node) return Wire_Id;
-
procedure Create_Object
(Syn_Inst : Synth_Instance_Acc; Decl : Iir; Val : Value_Acc);
diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb
index 4866b112b..e512b948a 100644
--- a/src/synth/synth-decls.adb
+++ b/src/synth/synth-decls.adb
@@ -55,7 +55,7 @@ package body Synth.Decls is
else
Value := Build_Signal (Build_Context, Name, W);
end if;
- Wire_Id_Table.Table (Val.W).Gate := Value;
+ Set_Wire_Gate (Val.W, Value);
when others =>
raise Internal_Error;
end case;
diff --git a/src/synth/synth-environment.adb b/src/synth/synth-environment.adb
index 536ea5710..ce8bb6983 100644
--- a/src/synth/synth-environment.adb
+++ b/src/synth/synth-environment.adb
@@ -24,6 +24,35 @@ with Netlists.Builders; use Netlists.Builders;
with Synth.Inference;
package body Synth.Environment is
+ procedure Set_Wire_Mark (Wid : Wire_Id; Mark : Boolean := True) is
+ begin
+ Wire_Id_Table.Table (Wid).Mark_Flag := Mark;
+ end Set_Wire_Mark;
+
+ function Get_Wire_Mark (Wid : Wire_Id) return Boolean is
+ begin
+ return Wire_Id_Table.Table (Wid).Mark_Flag;
+ end Get_Wire_Mark;
+
+ function Alloc_Wire (Kind : Wire_Kind; Obj : Source.Syn_Src)
+ return Wire_Id is
+ begin
+ Wire_Id_Table.Append ((Kind => Kind,
+ Mark_Flag => False,
+ Decl => Obj,
+ Gate => No_Net,
+ Cur_Assign => No_Seq_Assign));
+ return Wire_Id_Table.Last;
+ end Alloc_Wire;
+
+ procedure Set_Wire_Gate (Wid : Wire_Id; Gate : Net) is
+ begin
+ -- Cannot override a gate.
+ pragma Assert (Wire_Id_Table.Table (Wid).Gate = No_Net);
+
+ Wire_Id_Table.Table (Wid).Gate := Gate;
+ end Set_Wire_Gate;
+
function Get_Wire_Id (W : Seq_Assign) return Wire_Id is
begin
return Assign_Table.Table (W).Id;
diff --git a/src/synth/synth-environment.ads b/src/synth/synth-environment.ads
index d40eeb6f6..0a4ea415b 100644
--- a/src/synth/synth-environment.ads
+++ b/src/synth/synth-environment.ads
@@ -51,25 +51,18 @@ package Synth.Environment is
type Seq_Assign is new Uns32;
No_Seq_Assign : constant Seq_Assign := 0;
- -- A Wire_Id represents a bit or a vector.
- type Wire_Id_Record is record
- -- Kind of wire: signal, variable...
- -- Set at initialization and cannot be changed.
- Kind : Wire_Kind;
+ type Conc_Assign is new Uns32;
+ No_Conc_Assign : constant Conc_Assign := 0;
- -- Used in various algorithms: a flag on a wire. This flag must be
- -- cleared after usage.
- Mark_Flag : Boolean;
+ -- A Wire_Id represents a bit or a vector.
+ type Wire_Id_Record is private;
- -- Source node that created the wire.
- Decl : Source.Syn_Src;
+ function Alloc_Wire (Kind : Wire_Kind; Obj : Source.Syn_Src)
+ return Wire_Id;
- -- The initial net for the wire.
- Gate : Net;
-
- -- Current assignment (if there is one).
- Cur_Assign : Seq_Assign;
- end record;
+ -- Set the gate for a wire.
+ -- The gate represent the current value. It is usually an Id_Signal.
+ procedure Set_Wire_Gate (Wid : Wire_Id; Gate : Net);
-- The current value of WID. For variables, this is the last assigned
-- value. For signals, this is the initial value.
@@ -78,7 +71,9 @@ package Synth.Environment is
-- The last assigned value to WID.
function Get_Last_Assigned_Value (Wid : Wire_Id) return Net;
- --
+ -- Read and write the mark flag.
+ function Get_Wire_Mark (Wid : Wire_Id) return Boolean;
+ procedure Set_Wire_Mark (Wid : Wire_Id; Mark : Boolean := True);
type Phi_Id is new Uns32;
No_Phi_Id : constant Phi_Id := 0;
@@ -131,12 +126,6 @@ package Synth.Environment is
function Current_Phi return Phi_Id;
pragma Inline (Current_Phi);
- package Wire_Id_Table is new Tables
- (Table_Component_Type => Wire_Id_Record,
- Table_Index_Type => Wire_Id,
- Table_Low_Bound => No_Wire_Id,
- Table_Initial => 1024);
-
package Assign_Table is new Tables
(Table_Component_Type => Seq_Assign_Record,
Table_Index_Type => Seq_Assign,
@@ -144,6 +133,25 @@ package Synth.Environment is
Table_Initial => 1024);
private
+ type Wire_Id_Record is record
+ -- Kind of wire: signal, variable...
+ -- Set at initialization and cannot be changed.
+ Kind : Wire_Kind;
+
+ -- Used in various algorithms: a flag on a wire. This flag must be
+ -- cleared after usage.
+ Mark_Flag : Boolean;
+
+ -- Source node that created the wire.
+ Decl : Source.Syn_Src;
+
+ -- The initial net for the wire.
+ Gate : Net;
+
+ -- Current assignment (if there is one).
+ Cur_Assign : Seq_Assign;
+ end record;
+
type Phi_Type is record
First : Seq_Assign;
Nbr : Uns32;
@@ -154,4 +162,10 @@ private
Table_Index_Type => Phi_Id,
Table_Low_Bound => No_Phi_Id,
Table_Initial => 16);
+
+ package Wire_Id_Table is new Tables
+ (Table_Component_Type => Wire_Id_Record,
+ Table_Index_Type => Wire_Id,
+ Table_Low_Bound => No_Wire_Id,
+ Table_Initial => 1024);
end Synth.Environment;
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb
index a45ed8590..d5d3f4bf3 100644
--- a/src/synth/synth-insts.adb
+++ b/src/synth/synth-insts.adb
@@ -429,7 +429,7 @@ package body Synth.Insts is
Value := Builders.Build_Signal
(Build_Context, New_Sname (No_Sname, Get_Identifier (Inter)),
Val.W_Bound.Len);
- Wire_Id_Table.Table (Val.W).Gate := Value;
+ Set_Wire_Gate (Val.W, Value);
when others =>
raise Internal_Error;
end case;
@@ -656,7 +656,7 @@ package body Synth.Insts is
case Val.Kind is
when Value_Wire =>
Val.W := Alloc_Wire (Wire_Input, Inter);
- Wire_Id_Table.Table (Val.W).Gate := Get_Output (Self_Inst, Idx);
+ Set_Wire_Gate (Val.W, Get_Output (Self_Inst, Idx));
Idx := Idx + 1;
when others =>
raise Internal_Error;
@@ -681,7 +681,7 @@ package body Synth.Insts is
Value := Builders.Build_Output (Build_Context, W);
Inp := Get_Input (Self_Inst, Idx);
Connect (Inp, Value);
- Wire_Id_Table.Table (Val.W).Gate := Value;
+ Set_Wire_Gate (Val.W, Value);
Idx := Idx + 1;
when others =>
raise Internal_Error;
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb
index 6fb9e9313..1f37f25bc 100644
--- a/src/synth/synth-stmts.adb
+++ b/src/synth/synth-stmts.adb
@@ -418,9 +418,9 @@ package body Synth.Stmts is
Asgn := Alts (I).Asgns;
while Asgn /= No_Seq_Assign loop
W := Get_Wire_Id (Asgn);
- if not Wire_Id_Table.Table (W).Mark_Flag then
+ if not Get_Wire_Mark (W) then
Res := Res + 1;
- Wire_Id_Table.Table (W).Mark_Flag := True;
+ Set_Wire_Mark (W, True);
end if;
Asgn := Get_Assign_Chain (Asgn);
end loop;
@@ -440,10 +440,10 @@ package body Synth.Stmts is
Asgn := Alts (I).Asgns;
while Asgn /= No_Seq_Assign loop
W := Get_Wire_Id (Asgn);
- if Wire_Id_Table.Table (W).Mark_Flag then
+ if Get_Wire_Mark (W) then
Arr (Idx) := W;
Idx := Idx + 1;
- Wire_Id_Table.Table (W).Mark_Flag := False;
+ Set_Wire_Mark (W, False);
end if;
Asgn := Get_Assign_Chain (Asgn);
end loop;
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 05:56:49 +0000