diff options
| -rw-r--r-- | testsuite/synth/psl02/verif3.vhdl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/testsuite/synth/psl02/verif3.vhdl b/testsuite/synth/psl02/verif3.vhdl index c1b262177..abc5ad220 100644 --- a/testsuite/synth/psl02/verif3.vhdl +++ b/testsuite/synth/psl02/verif3.vhdl @@ -1,4 +1,4 @@ -vunit verif2 (assert2(behav)) +vunit verif3 (assert2(behav)) { default clock is rising_edge(clk); assume always val < 10; |