diff options
| -rw-r--r-- | pyGHDL/dom/Names.py | 8 | ||||
| -rw-r--r-- | pyGHDL/dom/_Translate.py | 10 | ||||
| -rw-r--r-- | testsuite/pyunit/Current.vhdl | 3 |
3 files changed, 20 insertions, 1 deletions
diff --git a/pyGHDL/dom/Names.py b/pyGHDL/dom/Names.py index f98555681..acb9cd1d6 100644 --- a/pyGHDL/dom/Names.py +++ b/pyGHDL/dom/Names.py @@ -42,6 +42,7 @@ from pyVHDLModel.SyntaxModel import ( SelectedName as VHDLModel_SelectedName, AttributeName as VHDLModel_AttributeName, AllName as VHDLModel_AllName, + OpenName as VHDLModel_OpenName, Name, ) from pyGHDL.libghdl._types import Iir @@ -97,3 +98,10 @@ class AllName(VHDLModel_AllName, DOMMixin): def __init__(self, node: Iir, prefix: Name): super().__init__(prefix) DOMMixin.__init__(self, node) + + +@export +class OpenName(VHDLModel_OpenName, DOMMixin): + def __init__(self, node: Iir): + super().__init__() + DOMMixin.__init__(self, node) diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index e7e862039..ed2e32ce3 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -73,6 +73,7 @@ from pyGHDL.dom.Names import ( AttributeName, ParenthesisName, AllName, + OpenName, ) from pyGHDL.dom.Symbol import ( SimpleObjectOrFunctionCallSymbol, @@ -673,6 +674,15 @@ def GetMapAspect( actual = GetExpressionFromNode(nodes.Get_Actual(generic)) yield cls(generic, actual, formal) + elif kind is nodes.Iir_Kind.Association_Element_Open: + formalNode = nodes.Get_Formal(generic) + if formalNode is nodes.Null_Iir: + formal = None + else: + formal = GetNameFromNode(formalNode) + + open = OpenName(generic) + yield cls(generic, open, formal) else: pos = Position.parse(generic) raise DOMException( diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index 81887ae7f..b4906e211 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -165,7 +165,8 @@ begin begin inst4: entity work.counter4(rtl) port map ( - clk => Clock + clk => Clock, + value => open ); end block; |