diff options
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 72 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_arith.adb | 107 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 54 |
3 files changed, 221 insertions, 12 deletions
diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 17c70ddea..67ed3088d 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1457,18 +1457,66 @@ class Iir_Predefined: Ieee_Std_Logic_Arith_Add_Log_Uns_Slv = 474 Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv = 475 Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv = 476 - Ieee_Std_Logic_Misc_And_Reduce_Slv = 477 - Ieee_Std_Logic_Misc_And_Reduce_Suv = 478 - Ieee_Std_Logic_Misc_Nand_Reduce_Slv = 479 - Ieee_Std_Logic_Misc_Nand_Reduce_Suv = 480 - Ieee_Std_Logic_Misc_Or_Reduce_Slv = 481 - Ieee_Std_Logic_Misc_Or_Reduce_Suv = 482 - Ieee_Std_Logic_Misc_Nor_Reduce_Slv = 483 - Ieee_Std_Logic_Misc_Nor_Reduce_Suv = 484 - Ieee_Std_Logic_Misc_Xor_Reduce_Slv = 485 - Ieee_Std_Logic_Misc_Xor_Reduce_Suv = 486 - Ieee_Std_Logic_Misc_Xnor_Reduce_Slv = 487 - Ieee_Std_Logic_Misc_Xnor_Reduce_Suv = 488 + Ieee_Std_Logic_Arith_Lt_Uns_Uns = 477 + Ieee_Std_Logic_Arith_Lt_Sgn_Sgn = 478 + Ieee_Std_Logic_Arith_Lt_Uns_Sgn = 479 + Ieee_Std_Logic_Arith_Lt_Sgn_Uns = 480 + Ieee_Std_Logic_Arith_Lt_Uns_Int = 481 + Ieee_Std_Logic_Arith_Lt_Int_Uns = 482 + Ieee_Std_Logic_Arith_Lt_Sgn_Int = 483 + Ieee_Std_Logic_Arith_Lt_Int_Sgn = 484 + Ieee_Std_Logic_Arith_Le_Uns_Uns = 485 + Ieee_Std_Logic_Arith_Le_Sgn_Sgn = 486 + Ieee_Std_Logic_Arith_Le_Uns_Sgn = 487 + Ieee_Std_Logic_Arith_Le_Sgn_Uns = 488 + Ieee_Std_Logic_Arith_Le_Uns_Int = 489 + Ieee_Std_Logic_Arith_Le_Int_Uns = 490 + Ieee_Std_Logic_Arith_Le_Sgn_Int = 491 + Ieee_Std_Logic_Arith_Le_Int_Sgn = 492 + Ieee_Std_Logic_Arith_Gt_Uns_Uns = 493 + Ieee_Std_Logic_Arith_Gt_Sgn_Sgn = 494 + Ieee_Std_Logic_Arith_Gt_Uns_Sgn = 495 + Ieee_Std_Logic_Arith_Gt_Sgn_Uns = 496 + Ieee_Std_Logic_Arith_Gt_Uns_Int = 497 + Ieee_Std_Logic_Arith_Gt_Int_Uns = 498 + Ieee_Std_Logic_Arith_Gt_Sgn_Int = 499 + Ieee_Std_Logic_Arith_Gt_Int_Sgn = 500 + Ieee_Std_Logic_Arith_Ge_Uns_Uns = 501 + Ieee_Std_Logic_Arith_Ge_Sgn_Sgn = 502 + Ieee_Std_Logic_Arith_Ge_Uns_Sgn = 503 + Ieee_Std_Logic_Arith_Ge_Sgn_Uns = 504 + Ieee_Std_Logic_Arith_Ge_Uns_Int = 505 + Ieee_Std_Logic_Arith_Ge_Int_Uns = 506 + Ieee_Std_Logic_Arith_Ge_Sgn_Int = 507 + Ieee_Std_Logic_Arith_Ge_Int_Sgn = 508 + Ieee_Std_Logic_Arith_Eq_Uns_Uns = 509 + Ieee_Std_Logic_Arith_Eq_Sgn_Sgn = 510 + Ieee_Std_Logic_Arith_Eq_Uns_Sgn = 511 + Ieee_Std_Logic_Arith_Eq_Sgn_Uns = 512 + Ieee_Std_Logic_Arith_Eq_Uns_Int = 513 + Ieee_Std_Logic_Arith_Eq_Int_Uns = 514 + Ieee_Std_Logic_Arith_Eq_Sgn_Int = 515 + Ieee_Std_Logic_Arith_Eq_Int_Sgn = 516 + Ieee_Std_Logic_Arith_Ne_Uns_Uns = 517 + Ieee_Std_Logic_Arith_Ne_Sgn_Sgn = 518 + Ieee_Std_Logic_Arith_Ne_Uns_Sgn = 519 + Ieee_Std_Logic_Arith_Ne_Sgn_Uns = 520 + Ieee_Std_Logic_Arith_Ne_Uns_Int = 521 + Ieee_Std_Logic_Arith_Ne_Int_Uns = 522 + Ieee_Std_Logic_Arith_Ne_Sgn_Int = 523 + Ieee_Std_Logic_Arith_Ne_Int_Sgn = 524 + Ieee_Std_Logic_Misc_And_Reduce_Slv = 525 + Ieee_Std_Logic_Misc_And_Reduce_Suv = 526 + Ieee_Std_Logic_Misc_Nand_Reduce_Slv = 527 + Ieee_Std_Logic_Misc_Nand_Reduce_Suv = 528 + Ieee_Std_Logic_Misc_Or_Reduce_Slv = 529 + Ieee_Std_Logic_Misc_Or_Reduce_Suv = 530 + Ieee_Std_Logic_Misc_Nor_Reduce_Slv = 531 + Ieee_Std_Logic_Misc_Nor_Reduce_Suv = 532 + Ieee_Std_Logic_Misc_Xor_Reduce_Slv = 533 + Ieee_Std_Logic_Misc_Xor_Reduce_Suv = 534 + Ieee_Std_Logic_Misc_Xnor_Reduce_Slv = 535 + Ieee_Std_Logic_Misc_Xnor_Reduce_Suv = 536 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location diff --git a/src/vhdl/vhdl-ieee-std_logic_arith.adb b/src/vhdl/vhdl-ieee-std_logic_arith.adb index a4183d9b4..4c2b517ec 100644 --- a/src/vhdl/vhdl-ieee-std_logic_arith.adb +++ b/src/vhdl/vhdl-ieee-std_logic_arith.adb @@ -39,6 +39,11 @@ package body Vhdl.Ieee.Std_Logic_Arith is array (Res_Arg_Kind, Conv_Arg_Kind, Conv_Arg_Kind) of Iir_Predefined_Functions; + subtype Cmp_Arg_Kind is Arg_Kind range Type_Signed .. Type_Int; + + type Cmp_Pattern_Type is array (Cmp_Arg_Kind, Cmp_Arg_Kind) + of Iir_Predefined_Functions; + Conv_Uns_Patterns : constant Conv_Pattern_Type := (Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Uns, @@ -168,6 +173,90 @@ package body Vhdl.Ieee.Std_Logic_Arith is others => (others => Iir_Predefined_None))); + Lt_Patterns : constant Cmp_Pattern_Type := + (Type_Unsigned => + (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Uns_Uns, + Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Uns_Sgn, + Type_Int => Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Uns_Int), + Type_Signed => + (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Sgn_Uns, + Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Sgn_Sgn, + Type_Int => Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Sgn_Int), + Type_Int => + (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Int_Uns, + Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Int_Sgn, + others => Iir_Predefined_None)); + + Le_Patterns : constant Cmp_Pattern_Type := + (Type_Unsigned => + (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Le_Uns_Uns, + Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Le_Uns_Sgn, + Type_Int => Iir_Predefined_Ieee_Std_Logic_Arith_Le_Uns_Int), + Type_Signed => + (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Le_Sgn_Uns, + Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Le_Sgn_Sgn, + Type_Int => Iir_Predefined_Ieee_Std_Logic_Arith_Le_Sgn_Int), + Type_Int => + (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Le_Int_Uns, + Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Le_Int_Sgn, + others => Iir_Predefined_None)); + + Gt_Patterns : constant Cmp_Pattern_Type := + (Type_Unsigned => + (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Uns_Uns, + Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Uns_Sgn, + Type_Int => Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Uns_Int), + Type_Signed => + (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Sgn_Uns, + Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Sgn_Sgn, + Type_Int => Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Sgn_Int), + Type_Int => + (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Int_Uns, + Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Int_Sgn, + others => Iir_Predefined_None)); + + Ge_Patterns : constant Cmp_Pattern_Type := + (Type_Unsigned => + (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Uns_Uns, + Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Uns_Sgn, + Type_Int => Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Uns_Int), + Type_Signed => + (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Sgn_Uns, + Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Sgn_Sgn, + Type_Int => Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Sgn_Int), + Type_Int => + (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Int_Uns, + Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Int_Sgn, + others => Iir_Predefined_None)); + + Eq_Patterns : constant Cmp_Pattern_Type := + (Type_Unsigned => + (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Eq_Uns_Uns, + Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Eq_Uns_Sgn, + Type_Int => Iir_Predefined_Ieee_Std_Logic_Arith_Eq_Uns_Int), + Type_Signed => + (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Eq_Sgn_Uns, + Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Eq_Sgn_Sgn, + Type_Int => Iir_Predefined_Ieee_Std_Logic_Arith_Eq_Sgn_Int), + Type_Int => + (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Eq_Int_Uns, + Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Eq_Int_Sgn, + others => Iir_Predefined_None)); + + Ne_Patterns : constant Cmp_Pattern_Type := + (Type_Unsigned => + (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Uns_Uns, + Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Uns_Sgn, + Type_Int => Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Uns_Int), + Type_Signed => + (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Sgn_Uns, + Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Sgn_Sgn, + Type_Int => Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Sgn_Int), + Type_Int => + (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Int_Uns, + Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Int_Sgn, + others => Iir_Predefined_None)); + Error : exception; procedure Extract_Declarations (Pkg : Iir_Package_Declaration) @@ -213,6 +302,12 @@ package body Vhdl.Ieee.Std_Logic_Arith is return Pats (Res_Kind, Arg1_Kind, Arg2_Kind); end Handle_Bin; + function Handle_Cmp (Pats : Cmp_Pattern_Type) + return Iir_Predefined_Functions is + begin + return Pats (Arg1_Kind, Arg2_Kind); + end Handle_Cmp; + Def : Iir_Predefined_Functions; begin Decl := Get_Declaration_Chain (Pkg); @@ -290,6 +385,18 @@ package body Vhdl.Ieee.Std_Logic_Arith is Def := Handle_Conv (Conv_Uns_Patterns); when Name_Conv_Std_Logic_Vector => Def := Handle_Conv (Conv_Vec_Patterns); + when Name_Op_Less => + Def := Handle_Cmp (Lt_Patterns); + when Name_Op_Less_Equal => + Def := Handle_Cmp (Le_Patterns); + when Name_Op_Greater => + Def := Handle_Cmp (Gt_Patterns); + when Name_Op_Greater_Equal => + Def := Handle_Cmp (Ge_Patterns); + when Name_Op_Equality => + Def := Handle_Cmp (Eq_Patterns); + when Name_Op_Inequality => + Def := Handle_Cmp (Ne_Patterns); when others => null; end case; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 628f1b2f8..c6f7d0891 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5818,6 +5818,60 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv, Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv, + Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Uns_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Sgn_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Uns_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Sgn_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Uns_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Int_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Sgn_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Lt_Int_Sgn, + + Iir_Predefined_Ieee_Std_Logic_Arith_Le_Uns_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Le_Sgn_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Le_Uns_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Le_Sgn_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Le_Uns_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Le_Int_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Le_Sgn_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Le_Int_Sgn, + + Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Uns_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Sgn_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Uns_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Sgn_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Uns_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Int_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Sgn_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Gt_Int_Sgn, + + Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Uns_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Sgn_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Uns_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Sgn_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Uns_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Int_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Sgn_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Ge_Int_Sgn, + + Iir_Predefined_Ieee_Std_Logic_Arith_Eq_Uns_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Eq_Sgn_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Eq_Uns_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Eq_Sgn_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Eq_Uns_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Eq_Int_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Eq_Sgn_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Eq_Int_Sgn, + + Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Uns_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Sgn_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Uns_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Sgn_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Uns_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Int_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Sgn_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Ne_Int_Sgn, + -- std_logic_misc (synopsys extension) Iir_Predefined_Ieee_Std_Logic_Misc_And_Reduce_Slv, Iir_Predefined_Ieee_Std_Logic_Misc_And_Reduce_Suv, |