diff options
| -rw-r--r-- | testsuite/synth/issue1114/ent.vhdl | 24 | ||||
| -rwxr-xr-x | testsuite/synth/issue1114/testsuite.sh | 11 |
2 files changed, 35 insertions, 0 deletions
diff --git a/testsuite/synth/issue1114/ent.vhdl b/testsuite/synth/issue1114/ent.vhdl new file mode 100644 index 000000000..05aaa8952 --- /dev/null +++ b/testsuite/synth/issue1114/ent.vhdl @@ -0,0 +1,24 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + port ( + clk : in std_logic; + i : in std_logic_vector(7 downto 0); + o : out std_logic_vector(3 downto 0) + ); +end; + +architecture a of ent is + function invert(x : std_logic_vector) return std_logic_vector is + begin + return not x; + end function; +begin + process(clk) + begin + if rising_edge(clk) then + o <= invert(i)(3 downto 0); + end if; + end process; +end; diff --git a/testsuite/synth/issue1114/testsuite.sh b/testsuite/synth/issue1114/testsuite.sh new file mode 100755 index 000000000..976a2eec7 --- /dev/null +++ b/testsuite/synth/issue1114/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in ent; do + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl + clean +done + +echo "Test successful" |