diff options
| -rw-r--r-- | testsuite/synth/issue1572/ent.psl | 11 | ||||
| -rw-r--r-- | testsuite/synth/issue1572/ent.vhdl | 17 | ||||
| -rwxr-xr-x | testsuite/synth/issue1572/testsuite.sh | 7 |
3 files changed, 35 insertions, 0 deletions
diff --git a/testsuite/synth/issue1572/ent.psl b/testsuite/synth/issue1572/ent.psl new file mode 100644 index 000000000..87b1a8c48 --- /dev/null +++ b/testsuite/synth/issue1572/ent.psl @@ -0,0 +1,11 @@ +vunit i_ent(ent(synthesis)) +{ + default clock is rising_edge(clk_i); + + process (all) + variable num_colors : integer_vector(0 to 7); + begin + num_colors := (others => 0); + num_colors(to_integer(u0)) := num_colors(to_integer(u0)) + 1; + end process; +} diff --git a/testsuite/synth/issue1572/ent.vhdl b/testsuite/synth/issue1572/ent.vhdl new file mode 100644 index 000000000..b8b67745c --- /dev/null +++ b/testsuite/synth/issue1572/ent.vhdl @@ -0,0 +1,17 @@ +-- ent.vhd +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std_unsigned.all; + +entity ent is + port ( + clk_i : in std_logic; + done_o : out std_logic + ); +end entity ent; + +architecture synthesis of ent is + signal u0 : std_logic_vector(2 downto 0) := "101"; +begin + done_o <= '0'; +end architecture synthesis; diff --git a/testsuite/synth/issue1572/testsuite.sh b/testsuite/synth/issue1572/testsuite.sh new file mode 100755 index 000000000..75017b449 --- /dev/null +++ b/testsuite/synth/issue1572/testsuite.sh @@ -0,0 +1,7 @@ +#! /bin/sh + +. ../../testenv.sh + +synth --std=08 ent.vhdl ent.psl -e > syn_ent.vhdl + +echo "Test successful" |