diff options
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 49 | ||||
| -rw-r--r-- | src/synth/synth-oper.adb | 3 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_unsigned.adb | 9 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 6 |
4 files changed, 44 insertions, 23 deletions
diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 08feba5fc..d684700a6 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1176,28 +1176,33 @@ class Iir_Predefined: Ieee_Std_Logic_Unsigned_Add_Int_Slv = 297 Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 298 Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 299 - Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 300 - Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 301 - Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 302 - Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 303 - Ieee_Std_Logic_Unsigned_Le_Slv_Int = 304 - Ieee_Std_Logic_Unsigned_Le_Int_Slv = 305 - Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 306 - Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 307 - Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 308 - Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 309 - Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 310 - Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 311 - Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 312 - Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 313 - Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 314 - Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 315 - Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 316 - Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 317 - Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 318 - Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 319 - Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 320 - Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 321 + Ieee_Std_Logic_Unsigned_Sub_Slv_Slv = 300 + Ieee_Std_Logic_Unsigned_Sub_Slv_Int = 301 + Ieee_Std_Logic_Unsigned_Sub_Int_Slv = 302 + Ieee_Std_Logic_Unsigned_Sub_Slv_Sl = 303 + Ieee_Std_Logic_Unsigned_Sub_Sl_Slv = 304 + Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 305 + Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 306 + Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 307 + Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 308 + Ieee_Std_Logic_Unsigned_Le_Slv_Int = 309 + Ieee_Std_Logic_Unsigned_Le_Int_Slv = 310 + Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 311 + Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 312 + Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 313 + Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 314 + Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 315 + Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 316 + Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 317 + Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 318 + Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 319 + Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 320 + Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 321 + Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 322 + Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 323 + Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 324 + Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 325 + Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 326 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index bdea830f1..62bc1a51e 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -507,7 +507,8 @@ package body Synth.Oper is -- "+" (Signed, Signed) return Synth_Dyadic_Sgn (Id_Add, True); - when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat => + when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int => -- "-" (Unsigned, Natural) return Synth_Dyadic_Uns_Nat (Id_Sub); when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns => diff --git a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb index dafbf7dad..7e2b86c02 100644 --- a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb +++ b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb @@ -58,6 +58,13 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is Arg_Slv_Sl => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl, Arg_Sl_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Sl_Slv); + Sub_Patterns : constant Binary_Pattern_Type := + (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv, + Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int, + Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Int_Slv, + Arg_Slv_Sl => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Sl, + Arg_Sl_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Sl_Slv); + Error : exception; procedure Extract_Declarations (Pkg : Iir_Package_Declaration) @@ -140,6 +147,8 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is Handle_Binary (Le_Patterns); when Name_Op_Plus => Handle_Binary (Add_Patterns); + when Name_Op_Minus => + Handle_Binary (Sub_Patterns); when others => null; end case; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 840f0bb70..f903a4c4d 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5063,6 +5063,12 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl, Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Sl_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Int_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Sl, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Sl_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Int_Slv, |