diff options
| -rw-r--r-- | src/vhdl/sem_psl.adb | 25 | ||||
| -rw-r--r-- | src/vhdl/sem_psl.ads | 2 | ||||
| -rw-r--r-- | src/vhdl/sem_stmts.adb | 43 |
3 files changed, 46 insertions, 24 deletions
diff --git a/src/vhdl/sem_psl.adb b/src/vhdl/sem_psl.adb index cae63f740..8811a0c28 100644 --- a/src/vhdl/sem_psl.adb +++ b/src/vhdl/sem_psl.adb @@ -478,19 +478,38 @@ package body Sem_Psl is Close_Declarative_Region; end Sem_Psl_Declaration; - procedure Sem_Psl_Assert_Statement (Stmt : Iir) + function Sem_Psl_Assert_Statement (Stmt : Iir) return Iir is Prop : Node; Clk : Node; + Res : Iir; begin Prop := Get_Psl_Property (Stmt); Prop := Sem_Property (Prop, True); Extract_Clock (Prop, Clk); - Set_Psl_Property (Stmt, Prop); -- Sem report and severity expressions. Sem_Report_Statement (Stmt); + if Get_Kind (Prop) = N_HDL_Expr + and then Get_Kind (Stmt) = Iir_Kind_Psl_Assert_Statement + then + -- This is a simple assertion. Convert to a non-PSL statement, as + -- the handling is simpler (and the assertion doesn't need a clock). + Res := Create_Iir (Iir_Kind_Concurrent_Assertion_Statement); + Set_Location (Res, Get_Location (Stmt)); + Set_Assertion_Condition (Res, Get_HDL_Node (Prop)); + Set_Label (Res, Get_Label (Stmt)); + Set_Severity_Expression (Res, Get_Severity_Expression (Stmt)); + Set_Report_Expression (Res, Get_Report_Expression (Stmt)); + Set_Postponed_Flag (Res, False); + Free_Iir (Stmt); + pragma Assert (Clk = Null_Node); + return Res; + else + Set_Psl_Property (Stmt, Prop); + end if; + -- Properties must be clocked. if Clk = Null_Node then if Current_Psl_Default_Clock = Null_Iir then @@ -504,6 +523,8 @@ package body Sem_Psl is -- Check simple subset restrictions. PSL.Subsets.Check_Simple (Prop); + + return Stmt; end Sem_Psl_Assert_Statement; procedure Sem_Psl_Default_Clock (Stmt : Iir) diff --git a/src/vhdl/sem_psl.ads b/src/vhdl/sem_psl.ads index 59df96f7f..25663a244 100644 --- a/src/vhdl/sem_psl.ads +++ b/src/vhdl/sem_psl.ads @@ -20,7 +20,7 @@ with Iirs; use Iirs; package Sem_Psl is procedure Sem_Psl_Declaration (Stmt : Iir); - procedure Sem_Psl_Assert_Statement (Stmt : Iir); + function Sem_Psl_Assert_Statement (Stmt : Iir) return Iir; procedure Sem_Psl_Default_Clock (Stmt : Iir); function Sem_Psl_Name (Name : Iir) return Iir; end Sem_Psl; diff --git a/src/vhdl/sem_stmts.adb b/src/vhdl/sem_stmts.adb index 714336212..e363c0da2 100644 --- a/src/vhdl/sem_stmts.adb +++ b/src/vhdl/sem_stmts.adb @@ -1845,6 +1845,8 @@ package body Sem_Stmts is Is_Passive : constant Boolean := Get_Kind (Parent) = Iir_Kind_Entity_Declaration; El: Iir; + New_El : Iir; + Next_El : Iir; procedure No_Generate_Statement is begin @@ -1864,6 +1866,8 @@ package body Sem_Stmts is Prev_El := Null_Iir; while El /= Null_Iir loop Current_Concurrent_Statement := El; + New_El := El; + Next_El := Get_Chain (El); case Get_Kind (El) is when Iir_Kind_Concurrent_Conditional_Signal_Assignment => @@ -1900,29 +1904,13 @@ package body Sem_Stmts is No_Generate_Statement; Sem_For_Generate_Statement (El); when Iir_Kind_Concurrent_Procedure_Call_Statement => - declare - Next_El : Iir; - N_Stmt : Iir; - begin - Next_El := Get_Chain (El); - N_Stmt := Sem_Concurrent_Procedure_Call_Statement - (El, Is_Passive); - if N_Stmt /= El then - -- Replace this node. - El := N_Stmt; - if Prev_El = Null_Iir then - Set_Concurrent_Statement_Chain (Parent, El); - else - Set_Chain (Prev_El, El); - end if; - Set_Chain (El, Next_El); - end if; - end; + New_El := Sem_Concurrent_Procedure_Call_Statement + (El, Is_Passive); when Iir_Kind_Psl_Declaration => Sem_Psl.Sem_Psl_Declaration (El); when Iir_Kind_Psl_Assert_Statement | Iir_Kind_Psl_Cover_Statement => - Sem_Psl.Sem_Psl_Assert_Statement (El); + New_El := Sem_Psl.Sem_Psl_Assert_Statement (El); when Iir_Kind_Psl_Default_Clock => Sem_Psl.Sem_Psl_Default_Clock (El); when Iir_Kind_Simple_Simultaneous_Statement => @@ -1930,8 +1918,21 @@ package body Sem_Stmts is when others => Error_Kind ("sem_concurrent_statement_chain", El); end case; - Prev_El := El; - El := Get_Chain (El); + + if New_El /= El then + -- Replace this node. + if Prev_El = Null_Iir then + Set_Concurrent_Statement_Chain (Parent, New_El); + else + Set_Chain (Prev_El, New_El); + end if; + Set_Chain (New_El, Next_El); + Prev_El := New_El; + else + Prev_El := El; + end if; + + El := Next_El; end loop; Current_Concurrent_Statement := Prev_Concurrent_Statement; |