diff options
| -rw-r--r-- | src/vhdl/simulate/simul-elaboration.adb | 34 | ||||
| -rw-r--r-- | src/vhdl/simulate/simul-elaboration.ads | 2 | ||||
| -rw-r--r-- | src/vhdl/simulate/simul-environments.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/simulate/simul-simulation-main.adb | 4 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_expr.adb | 4 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_names.adb | 8 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_scopes.adb | 6 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_specs.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-sem_types.adb | 6 | ||||
| -rw-r--r-- | src/vhdl/vhdl-utils.ads | 2 |
11 files changed, 36 insertions, 36 deletions
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb index b65614a6b..6ffe1ac58 100644 --- a/src/vhdl/simulate/simul-elaboration.adb +++ b/src/vhdl/simulate/simul-elaboration.adb @@ -904,7 +904,7 @@ package body Simul.Elaboration is end if; end Elaborate_Subtype_Indication_If_Anonymous; - -- LRM93 §12.3.1.3 Subtype Declarations + -- LRM93 12.3.1.3 Subtype Declarations -- The elaboration of a subtype indication creates a subtype. procedure Elaborate_Subtype_Indication (Instance : Block_Instance_Acc; Ind : Iir) @@ -948,7 +948,7 @@ package body Simul.Elaboration is end case; end Elaborate_Subtype_Indication; - -- LRM93 §12.3.1.2 Type Declarations. + -- LRM93 12.3.1.2 Type Declarations. procedure Elaborate_Type_Definition (Instance : Block_Instance_Acc; Def : Iir) is @@ -1015,7 +1015,7 @@ package body Simul.Elaboration is end case; end Elaborate_Type_Definition; - -- LRM93 §12.3.1.2 Type Declarations. + -- LRM93 12.3.1.2 Type Declarations. procedure Elaborate_Type_Declaration (Instance : Block_Instance_Acc; Decl : Iir_Type_Declaration) is @@ -1105,7 +1105,7 @@ package body Simul.Elaboration is begin Decl := Port_Chain; while Decl /= Null_Iir loop - -- LRM93 §12.2.3 + -- LRM93 12.2.3 -- The elaboration of a port declaration consists of elaborating the -- subtype indication and then creating a port of that subtype. Elaborate_Subtype_Indication_If_Anonymous (Instance, Get_Type (Decl)); @@ -1117,7 +1117,7 @@ package body Simul.Elaboration is end loop; end Elaborate_Port_Clause; - -- LRM93 §12.2.2 The generic Map Aspect + -- LRM93 12.2.2 The generic Map Aspect procedure Elaborate_Generic_Map_Aspect (Target_Instance : Block_Instance_Acc; Local_Instance : Block_Instance_Acc; @@ -1279,7 +1279,7 @@ package body Simul.Elaboration is end Elab_Connect; -- LRM93 12.2.3 The Port Clause - -- LRM93 §12.2.4 The Port Map Aspect + -- LRM93 12.2.4 The Port Map Aspect procedure Elaborate_Port_Map_Aspect (Formal_Instance : Block_Instance_Acc; Actual_Instance : Block_Instance_Acc; @@ -1425,7 +1425,7 @@ package body Simul.Elaboration is end loop; end Elaborate_Port_Map_Aspect; - -- LRM93 §12.2 Elaboration of a block header + -- LRM93 12.2 Elaboration of a block header -- Elaboration of a block header consists of the elaboration of the -- generic clause, the generic map aspect, the port clause, and the port -- map aspect, in that order. @@ -1464,7 +1464,7 @@ package body Simul.Elaboration is Instance => Instance)); end Elaborate_Guard_Signal; - -- LRM93 §12.4.1 Block statements. + -- LRM93 12.4.1 Block statements. procedure Elaborate_Block_Statement (Instance : Block_Instance_Acc; Block : Iir_Block_Statement) is @@ -1599,7 +1599,7 @@ package body Simul.Elaboration is end; end Create_Default_Association; - -- LRM93 §12.4.3 + -- LRM93 12.4.3 function Is_Fully_Bound (Conf : Iir) return Boolean is Binding : Iir; @@ -1854,7 +1854,7 @@ package body Simul.Elaboration is end if; end Elaborate_Psl_Directive; - -- LRM93 §12.4 Elaboration of a Statement Part. + -- LRM93 12.4 Elaboration of a Statement Part. procedure Elaborate_Concurrent_Statement_Part (Instance : Block_Instance_Acc; Stmt_Chain: Iir) is @@ -1953,7 +1953,7 @@ package body Simul.Elaboration is return Val; end Elaborate_Default_Value; - -- LRM93 §12.3.1.1 Subprogram Declaration and Bodies + -- LRM93 12.3.1.1 Subprogram Declaration and Bodies procedure Elaborate_Interface_List (Instance : Block_Instance_Acc; Inter_Chain : Iir) is @@ -1979,7 +1979,7 @@ package body Simul.Elaboration is end loop; end Elaborate_Interface_List; - -- LRM93 §12.3.1.1 Subprogram Declaration and Bodies + -- LRM93 12.3.1.1 Subprogram Declaration and Bodies procedure Elaborate_Subprogram_Declaration (Instance : Block_Instance_Acc; Decl : Iir) is @@ -2390,7 +2390,7 @@ package body Simul.Elaboration is Unshare_Bounds (Res, Instance_Pool); end Elaborate_Alias_Declaration; - -- LRM93 §12.3.2.3 Disconnection Specifications + -- LRM93 12.3.2.3 Disconnection Specifications procedure Elaborate_Disconnection_Specification (Instance : Block_Instance_Acc; Decl : Iir_Disconnection_Specification) @@ -2401,7 +2401,7 @@ package body Simul.Elaboration is Sig : Iir; Val : Iir_Value_Literal_Acc; begin - -- LRM93 §12.3.2.3 + -- LRM93 12.3.2.3 -- Elaboration of a disconnection specification proceeds as follows: -- 2. The time expression is evaluated to determine the disconnection -- time for drivers of the affected signals. @@ -2416,7 +2416,7 @@ package body Simul.Elaboration is Error_Msg_Sem (+Decl, "time must be non-negative"); end if; - -- LRM93 §12.3.2.3 + -- LRM93 12.3.2.3 -- 1. The guarded signal specification is elaborated in order to -- identify the signals affected by the disconnection specification. -- @@ -2489,7 +2489,7 @@ package body Simul.Elaboration is Elaborate_Subtype_Indication (Instance, Ind); end Elaborate_Declaration_Type; - -- LRM93 §12.3.1 Elaboration of a declaration + -- LRM93 12.3.1 Elaboration of a declaration procedure Elaborate_Declaration (Instance : Block_Instance_Acc; Decl : Iir) is Expr_Mark : Mark_Type; @@ -2790,7 +2790,7 @@ package body Simul.Elaboration is end loop; end Finalize_Declarative_Part; - -- LRM93 §12.3 Elaboration of a Declarative Part + -- LRM93 12.3 Elaboration of a Declarative Part procedure Elaborate_Declarative_Part (Instance : Block_Instance_Acc; Decl_Chain : Iir) is diff --git a/src/vhdl/simulate/simul-elaboration.ads b/src/vhdl/simulate/simul-elaboration.ads index 63fd11157..cc89d7bc0 100644 --- a/src/vhdl/simulate/simul-elaboration.ads +++ b/src/vhdl/simulate/simul-elaboration.ads @@ -66,7 +66,7 @@ package Simul.Elaboration is (Block: Block_Instance_Acc; Decl: Iir; Init : Init_Value_Kind) return Iir_Value_Literal_Acc; - -- LRM93 §12.3.1.3 Subtype Declarations + -- LRM93 12.3.1.3 Subtype Declarations -- The elaboration of a subtype indication creates a subtype. -- Used for allocator. procedure Elaborate_Subtype_Indication diff --git a/src/vhdl/simulate/simul-environments.adb b/src/vhdl/simulate/simul-environments.adb index 5e28441cf..cd8783d6b 100644 --- a/src/vhdl/simulate/simul-environments.adb +++ b/src/vhdl/simulate/simul-environments.adb @@ -145,7 +145,7 @@ package body Simul.Environments is raise Constraint_Error; end if; when Iir_Value_Array => - -- LRM93 §7.2.2 + -- LRM93 7.2.2 -- For discrete array types, the relation < (less than) is defined -- such as the left operand is less than the right operand if -- and only if: diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb index 956d0f3dc..a221c9e36 100644 --- a/src/vhdl/simulate/simul-simulation-main.adb +++ b/src/vhdl/simulate/simul-simulation-main.adb @@ -316,7 +316,7 @@ package body Simul.Simulation.Main is raise Internal_Error; end case; - -- LRM93 §12.4.4 Other Concurrent Statements + -- LRM93 12.4.4 Other Concurrent Statements -- All other concurrent statements are either process -- statements or are statements for which there is an -- equivalent process statement. @@ -820,7 +820,7 @@ package body Simul.Simulation.Main is else Src := Formal_Expr; end if; - -- LRM93 §12.6.2 + -- LRM93 12.6.2 -- A signal is said to be active [...] if one of its source -- is active. Connect (Local_Expr, Src, Connect_Source); diff --git a/src/vhdl/vhdl-sem.adb b/src/vhdl/vhdl-sem.adb index 595f5d494..ada48e53a 100644 --- a/src/vhdl/vhdl-sem.adb +++ b/src/vhdl/vhdl-sem.adb @@ -1144,7 +1144,7 @@ package body Vhdl.Sem is Error_Kind ("sem_block_configuration", Father); end case; - -- LRM93 §10.1 + -- LRM93 10.1 -- 10. A block configuration Sem_Scopes.Open_Scope_Extension; diff --git a/src/vhdl/vhdl-sem_expr.adb b/src/vhdl/vhdl-sem_expr.adb index e00aaadff..2e5afd86d 100644 --- a/src/vhdl/vhdl-sem_expr.adb +++ b/src/vhdl/vhdl-sem_expr.adb @@ -3024,7 +3024,7 @@ package body Vhdl.Sem_Expr is -- emitted for a case stmt. -- FIXME: what about individual associations? if not Is_Case_Stmt then - -- LRM93 §7.3.2.2 + -- LRM93 7.3.2.2 -- A named association of an array aggregate is allowed to have -- a choice that is not locally static, or likewise a choice that -- is a null range, only if the aggregate includes a single @@ -4536,7 +4536,7 @@ package body Vhdl.Sem_Expr is Lib : Iir; Cur_Lib : Iir; begin - -- LRM93 §2.6 + -- LRM93 2.6 -- Within a package declaration that contains the declaration -- of a deferred constant, and within the body of that package, -- before the end of the corresponding full declaration, the diff --git a/src/vhdl/vhdl-sem_names.adb b/src/vhdl/vhdl-sem_names.adb index 17db8ba99..b9bf11940 100644 --- a/src/vhdl/vhdl-sem_names.adb +++ b/src/vhdl/vhdl-sem_names.adb @@ -639,7 +639,7 @@ package body Vhdl.Sem_Names is begin Expr_Staticness := Locally; - -- LRM93 §6.4: there must be one such expression for each index + -- LRM93 6.4: there must be one such expression for each index -- position of the array and each expression must be of the -- type of the corresponding index. -- Loop on the indexes. @@ -2178,7 +2178,7 @@ package body Vhdl.Sem_Names is Set_Named_Entity (Name, Res); end Sem_Simple_Name; - -- LRM93 §6.3 + -- LRM93 6.3 -- Selected Names. procedure Sem_Selected_Name (Name: Iir; Keep_Alias : Boolean := False; Soft : Boolean := False) @@ -2443,7 +2443,7 @@ package body Vhdl.Sem_Names is | Iir_Kind_For_Generate_Statement | Iir_Kind_Block_Statement | Iir_Kind_For_Loop_Statement => - -- LRM93 §6.3 + -- LRM93 6.3 -- An expanded name denotes a named entity declared immediatly -- within a named construct if the prefix that is an entity -- interface, an architecture, a subprogram, a block statement, @@ -4402,7 +4402,7 @@ package body Vhdl.Sem_Names is Set_Named_Entity (Attr, Res); end Sem_Attribute_Name; - -- LRM93 §6 + -- LRM93 6 procedure Sem_Name (Name : Iir; Keep_Alias : Boolean := False) is begin -- Exit now if NAME was already analyzed. diff --git a/src/vhdl/vhdl-sem_scopes.adb b/src/vhdl/vhdl-sem_scopes.adb index 6e761edda..73f112db0 100644 --- a/src/vhdl/vhdl-sem_scopes.adb +++ b/src/vhdl/vhdl-sem_scopes.adb @@ -913,7 +913,7 @@ package body Vhdl.Sem_Scopes is else -- There is already a declaration in the current scope. if Potentially then - -- LRM93 §10.4 item #1 + -- LRM93 10.4 item #1 -- Discard the new and potentially visible declaration. -- However, add the type. -- FIXME: Add_In_Visible_List (Ident, Decl); @@ -950,7 +950,7 @@ package body Vhdl.Sem_Scopes is -- None of the two declarations are potentially visible, ie -- both are visible. - -- LRM §10.3: + -- LRM 10.3: -- Two declarations that occur immediately within the same -- declarative region must not be homographs, -- FIXME: unless one of them is the implicit declaration of a @@ -965,7 +965,7 @@ package body Vhdl.Sem_Scopes is return; else -- Homograph, not in the same scope. - -- LRM §10.3: + -- LRM93 10.3: -- A declaration is said to be hidden within (part of) an inner -- declarative region if the inner region contains an homograph -- of this declaration; the outer declaration is the hidden diff --git a/src/vhdl/vhdl-sem_specs.adb b/src/vhdl/vhdl-sem_specs.adb index 5b1f54a67..fb1eb4812 100644 --- a/src/vhdl/vhdl-sem_specs.adb +++ b/src/vhdl/vhdl-sem_specs.adb @@ -2010,7 +2010,7 @@ package body Vhdl.Sem_Specs is end if; end Create_Default_Map_Aspect; - -- LRM93 §5.2.2 + -- LRM93 5.2.2 function Get_Visible_Entity_Declaration (Comp: Iir_Component_Declaration) return Iir_Design_Unit is diff --git a/src/vhdl/vhdl-sem_types.adb b/src/vhdl/vhdl-sem_types.adb index 400438d41..cfdecc1be 100644 --- a/src/vhdl/vhdl-sem_types.adb +++ b/src/vhdl/vhdl-sem_types.adb @@ -465,7 +465,7 @@ package body Vhdl.Sem_Types is Val := Eval_Physical_Literal (Val); Set_Physical_Literal (Unit, Val); - -- LRM93 §3.1 + -- LRM93 3.1 -- The position number of unit names need not lie within the range -- specified by the range constraint. -- GHDL: this was not true in VHDL87. @@ -554,7 +554,7 @@ package body Vhdl.Sem_Types is Check_No_File_Type (El_Type, Def); Set_Signal_Type_Flag (Def, Get_Signal_Type_Flag (El_Type)); - -- LRM93 §3.2.1.1 + -- LRM93 3.2.1.1 -- The same requirement exists [must define a constrained -- array subtype] [...] for the element subtype indication -- of an array type definition, if the type of the array @@ -1100,7 +1100,7 @@ package body Vhdl.Sem_Types is Set_Signal_Type_Flag (Def, Get_Signal_Type_Flag (Base_Type)); - -- According to LRM93 §7.4.1, an unconstrained array type + -- According to LRM93 7.4.1, an unconstrained array type -- is not static. Set_Type_Staticness (Base_Type, None); Set_Type_Staticness (Def, Min (Staticness, diff --git a/src/vhdl/vhdl-utils.ads b/src/vhdl/vhdl-utils.ads index 08e7c6342..370a565fa 100644 --- a/src/vhdl/vhdl-utils.ads +++ b/src/vhdl/vhdl-utils.ads @@ -55,7 +55,7 @@ package Vhdl.Utils is function Get_Operator_Name (Op : Iir) return Name_Id; -- Get the longuest static prefix of EXPR. - -- See LRM §8.1 + -- See LRM93 8.1 function Get_Longuest_Static_Prefix (Expr: Iir) return Iir; -- Get the prefix of NAME, ie the declaration at the base of NAME. |