diff options
| -rw-r--r-- | pyGHDL/dom/Concurrent.py | 36 | ||||
| -rw-r--r-- | pyGHDL/dom/Sequential.py | 18 | ||||
| -rw-r--r-- | pyGHDL/dom/_Translate.py | 17 | ||||
| -rw-r--r-- | pyGHDL/dom/requirements.txt | 2 | ||||
| -rw-r--r-- | testsuite/pyunit/Current.vhdl | 10 |
5 files changed, 64 insertions, 19 deletions
diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 560acafb2..33973a455 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -57,6 +57,7 @@ from pyVHDLModel.SyntaxModel import ( WaveformElement as VHDLModel_WaveformElement, ConcurrentSimpleSignalAssignment as VHDLModel_ConcurrentSimpleSignalAssignment, ConcurrentProcedureCall as VHDLModel_ConcurrentProcedureCall, + ConcurrentAssertStatement as VHDLModel_ConcurrentAssertStatement, Name, ConcurrentStatement, SequentialStatement, @@ -258,10 +259,9 @@ class ProcessStatement(VHDLModel_ProcessStatement, DOMMixin): sensitivityList = None if hasSensitivityList: - pass - # FIXME: sensitity list - # sensitivityListNode = nodes.Get_Sensitivity_List(processNode) - # print("sensi", GetIirKindOfNode(sensitivityListNode)) + sensitivityList = [] + for item in utils.list_iter(nodes.Get_Sensitivity_List(processNode)): + sensitivityList.append(GetNameOfNode(item)) declaredItems = GetDeclaredItemsFromChainedNodes(nodes.Get_Declaration_Chain(processNode), "process", label) statements = GetSequentialStatementsFromChainedNodes( @@ -719,3 +719,31 @@ class ConcurrentProcedureCall(VHDLModel_ConcurrentProcedureCall, DOMMixin): parameterAssociations = GetParameterMapAspect(nodes.Get_Parameter_Association_Chain(callNode)) return cls(concurrentCallNode, label, procedureName, parameterAssociations) + + +@export +class ConcurrentAssertStatement(VHDLModel_ConcurrentAssertStatement, DOMMixin): + def __init__( + self, + assertNode: Iir, + condition: ExpressionUnion, + message: ExpressionUnion = None, + severity: ExpressionUnion = None, + label: str = None, + ): + super().__init__(condition, message, severity, label) + DOMMixin.__init__(self, assertNode) + + @classmethod + def parse(cls, assertNode: Iir, label: str) -> "ConcurrentAssertStatement": + from pyGHDL.dom._Translate import GetExpressionFromNode + + # FIXME: how to get the condition? + # assertNode is a Psl_Assert_Directive + condition = None # GetExpressionFromNode(nodes.Get_Assertion_Condition(assertNode)) + messageNode = nodes.Get_Report_Expression(assertNode) + message = None if messageNode is nodes.Null_Iir else GetExpressionFromNode(messageNode) + severityNode = nodes.Get_Severity_Expression(assertNode) + severity = None if severityNode is nodes.Null_Iir else GetExpressionFromNode(severityNode) + + return cls(assertNode, condition, message, severity, label) diff --git a/pyGHDL/dom/Sequential.py b/pyGHDL/dom/Sequential.py index 9e1af5b32..372939b28 100644 --- a/pyGHDL/dom/Sequential.py +++ b/pyGHDL/dom/Sequential.py @@ -54,6 +54,7 @@ from pyVHDLModel.SyntaxModel import ( SequentialProcedureCall as VHDLModel_SequentialProcedureCall, SequentialAssertStatement as VHDLModel_SequentialAssertStatement, SequentialReportStatement as VHDLModel_SequentialReportStatement, + NullStatement as VHDLModel_NullStatement, WaitStatement as VHDLModel_WaitStatement, Name, SequentialStatement, @@ -423,11 +424,11 @@ class SequentialProcedureCall(VHDLModel_SequentialProcedureCall, DOMMixin): def parse(cls, callNode: Iir, label: str) -> "SequentialProcedureCall": from pyGHDL.dom._Translate import GetNameFromNode, GetParameterMapAspect - call = nodes.Get_Procedure_Call(callNode) + cNode = nodes.Get_Procedure_Call(callNode) - prefix = nodes.Get_Prefix(call) + prefix = nodes.Get_Prefix(cNode) procedureName = GetNameFromNode(prefix) - parameterAssociations = GetParameterMapAspect(nodes.Get_Parameter_Association_Chain(callNode)) + parameterAssociations = GetParameterMapAspect(nodes.Get_Parameter_Association_Chain(cNode)) return cls(callNode, procedureName, parameterAssociations, label) @@ -482,6 +483,17 @@ class SequentialReportStatement(VHDLModel_SequentialReportStatement, DOMMixin): @export +class NullStatement(VHDLModel_NullStatement, DOMMixin): + def __init__( + self, + waitNode: Iir, + label: str = None, + ): + super().__init__(label) + DOMMixin.__init__(self, waitNode) + + +@export class WaitStatement(VHDLModel_WaitStatement, DOMMixin): def __init__( self, diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 723b13f69..fe66f2c98 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -42,6 +42,8 @@ from pyGHDL.dom.Sequential import ( SequentialAssertStatement, WaitStatement, SequentialSimpleSignalAssignment, + NullStatement, + SequentialProcedureCall, ) from pyVHDLModel.SyntaxModel import ( ConstraintUnion, @@ -164,6 +166,7 @@ from pyGHDL.dom.Concurrent import ( GenericAssociationItem, PortAssociationItem, ParameterAssociationItem, + ConcurrentAssertStatement, ) from pyGHDL.dom.Subprogram import Function, Procedure from pyGHDL.dom.Misc import Alias @@ -920,11 +923,7 @@ def GetConcurrentStatementsFromChainedNodes( elif kind == nodes.Iir_Kind.For_Generate_Statement: yield ForGenerateStatement.parse(statement, label) elif kind == nodes.Iir_Kind.Psl_Assert_Directive: - print( - "[NOT IMPLEMENTED] PSL assert directive (label: '{label}') at line {line}".format( - label=label, line=pos.Line - ) - ) + yield ConcurrentAssertStatement.parse(statement, label) else: raise DOMException( "Unknown statement of kind '{kind}' in {entity} '{name}' at {file}:{line}:{column}.".format( @@ -967,17 +966,13 @@ def GetSequentialStatementsFromChainedNodes( elif kind == nodes.Iir_Kind.Wait_Statement: yield WaitStatement.parse(statement, label) elif kind == nodes.Iir_Kind.Procedure_Call_Statement: - print( - "[NOT IMPLEMENTED] Procedure call (label: '{label}') at line {line}".format(label=label, line=pos.Line) - ) + yield SequentialProcedureCall.parse(statement, label) elif kind == nodes.Iir_Kind.Report_Statement: yield SequentialReportStatement.parse(statement, label) elif kind == nodes.Iir_Kind.Assertion_Statement: yield SequentialAssertStatement.parse(statement, label) elif kind == nodes.Iir_Kind.Null_Statement: - print( - "[NOT IMPLEMENTED] null statement (label: '{label}') at line {line}".format(label=label, line=pos.Line) - ) + yield NullStatement(statement, label) else: raise DOMException( "Unknown statement of kind '{kind}' in {entity} '{name}' at {file}:{line}:{column}.".format( diff --git a/pyGHDL/dom/requirements.txt b/pyGHDL/dom/requirements.txt index d296f0e96..18340052a 100644 --- a/pyGHDL/dom/requirements.txt +++ b/pyGHDL/dom/requirements.txt @@ -1,4 +1,4 @@ -r ../libghdl/requirements.txt -pyVHDLModel==0.11.5 +pyVHDLModel==0.12.0 #https://github.com/VHDL/pyVHDLModel/archive/dev.zip#pyVHDLModel diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index b4906e211..96e9433d9 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -94,6 +94,7 @@ begin Q <= D after 10 ns; else Q <= std_logic_vector(unsigned(Q) + 1); + counter.increment(1); end if; end if; @@ -133,6 +134,10 @@ begin a <= b; + assert false; + assert false report "some error"; + assert false severity warning; + assert false report "some note" severity note; inst1: entity work.counter1(rtl) generic map ( @@ -210,6 +215,11 @@ begin constant G7 : boolean := False; begin inst: component Case5689Dummy; + process + begin + null; + wait; + end process; when others => constant G8 : boolean := False; |