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-rw-r--r--testsuite/synth/issue2369/bug.vhdl15
-rwxr-xr-xtestsuite/synth/issue2369/testsuite.sh8
2 files changed, 23 insertions, 0 deletions
diff --git a/testsuite/synth/issue2369/bug.vhdl b/testsuite/synth/issue2369/bug.vhdl
new file mode 100644
index 000000000..df3e29787
--- /dev/null
+++ b/testsuite/synth/issue2369/bug.vhdl
@@ -0,0 +1,15 @@
+entity bug is
+ port (clk, x, y : in bit; z : out bit);
+end entity bug;
+
+architecture RTL of bug is
+begin
+
+process (clk)
+begin
+ if rising_edge(clk) then
+ z <= x when y else unaffected;
+ end if;
+end process;
+
+end architecture RTL;
diff --git a/testsuite/synth/issue2369/testsuite.sh b/testsuite/synth/issue2369/testsuite.sh
new file mode 100755
index 000000000..c355095b7
--- /dev/null
+++ b/testsuite/synth/issue2369/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth_only bug
+
+echo "Test successful"