diff options
-rw-r--r-- | testsuite/synth/issue1856/detector.psl | 12 | ||||
-rw-r--r-- | testsuite/synth/issue1856/pulse.vhdl | 43 | ||||
-rwxr-xr-x | testsuite/synth/issue1856/testsuite.sh | 8 |
3 files changed, 63 insertions, 0 deletions
diff --git a/testsuite/synth/issue1856/detector.psl b/testsuite/synth/issue1856/detector.psl new file mode 100644 index 000000000..3b2ae4f76 --- /dev/null +++ b/testsuite/synth/issue1856/detector.psl @@ -0,0 +1,12 @@ +vunit i_rising_pulse_detector(rising_pulse_detector(rising_pulse_detector_1)) +{ + + default clock is rising_edge(clk); + + constant idx : natural := 4; + + --working cover without generate + fc_output_4 : cover {output_pulse(idx) = '1'}; + +} + diff --git a/testsuite/synth/issue1856/pulse.vhdl b/testsuite/synth/issue1856/pulse.vhdl new file mode 100644 index 000000000..97f4dd893 --- /dev/null +++ b/testsuite/synth/issue1856/pulse.vhdl @@ -0,0 +1,43 @@ +-- Created on : 11/08/2021 +-- Author : Fabien Marteau <fabien.marteau@armadeus.com> +-- Copyright (c) ARMadeus systems 2015 + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.all; + + +Entity rising_pulse_detector is +generic( WAITPRETRIGG_CNT: natural := 1000); +port +( + clk : in std_logic; + rst : in std_logic; + + inputvec : in std_logic_vector(15 downto 0); + + output_pulse : out std_logic_vector(15 downto 0) + +); +end entity; + +Architecture rising_pulse_detector_1 of rising_pulse_detector is + + signal inputvec_old, inputvec_pulse : std_logic_vector(15 downto 0); + +begin + + output_pulse <= inputvec_pulse; + + process(clk, rst) + begin + if(rst = '1') then + inputvec_old <= (others => '0'); + inputvec_pulse <= (others => '0'); + elsif(rising_edge(clk)) then + inputvec_pulse <= (not inputvec_old) and inputvec; + inputvec_old <= inputvec; + end if; + end process; + +end architecture rising_pulse_detector_1; diff --git a/testsuite/synth/issue1856/testsuite.sh b/testsuite/synth/issue1856/testsuite.sh new file mode 100755 index 000000000..81eec2fc2 --- /dev/null +++ b/testsuite/synth/issue1856/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth pulse.vhdl detector.psl -e > syn_pulse.vhdl + +echo "Test successful" |