synth: add testcase for issue 34

13 files changed, 442 insertions, 0 deletions

diff --git a/testsuite/synth/issue34/module.vhdl b/testsuite/synth/issue34/module.vhdl
new file mode 100644
index 000000000..67f3dd4b3
--- /dev/null
+++ b/testsuite/synth/issue34/module.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity module is
+  port (
+    clk : in std_logic;
+    a : in std_logic_vector(7 downto 0);
+    b : out std_logic_vector(7 downto 0)
+  );
+end module;
+
+architecture rtl of module is
+begin
+  i_submodule : entity work.submodule
+  port map (
+    clk => clk,
+    a => a,
+    b => b
+  );
+end rtl;
diff --git a/testsuite/synth/issue34/repro_nat.vhdl b/testsuite/synth/issue34/repro_nat.vhdl
new file mode 100644
index 000000000..328c11781
--- /dev/null
+++ b/testsuite/synth/issue34/repro_nat.vhdl
@@ -0,0 +1,42 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity sub_nat is
+  port (
+    clk : in std_logic;
+    a : in natural;
+    b : out natural
+  );
+end sub_nat;
+
+architecture rtl of sub_nat is
+begin
+  process(clk)
+  begin
+    if rising_edge(clk) then
+      b <= a;
+    end if;
+  end process;
+end rtl;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro_nat is
+  port (
+    clk : in std_logic;
+    a : in natural;
+    b : out natural
+  );
+end repro_nat;
+
+architecture rtl of repro_nat is
+begin
+  i_sub_nat : entity work.sub_nat
+  port map (
+    clk => clk,
+    a => a,
+    b => b
+  );
+end rtl;
diff --git a/testsuite/synth/issue34/repro_rng1.vhdl b/testsuite/synth/issue34/repro_rng1.vhdl
new file mode 100644
index 000000000..9d5a70e04
--- /dev/null
+++ b/testsuite/synth/issue34/repro_rng1.vhdl
@@ -0,0 +1,42 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity sub_rng1 is
+  port (
+    clk : in std_logic;
+    a : in natural range 0 to 7;
+    b : out natural range 0 to 7
+  );
+end sub_rng1;
+
+architecture rtl of sub_rng1 is
+begin
+  process(clk)
+  begin
+    if rising_edge(clk) then
+      b <= a;
+    end if;
+  end process;
+end rtl;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro_rng1 is
+  port (
+    clk : in std_logic;
+    a : in natural range 0 to 7;
+    b : out natural range 0 to 7
+  );
+end repro_rng1;
+
+architecture rtl of repro_rng1 is
+begin
+  i_sub_rng1 : entity work.sub_rng1
+  port map (
+    clk => clk,
+    a => a,
+    b => b
+  );
+end rtl;
diff --git a/testsuite/synth/issue34/repro_sgn.vhdl b/testsuite/synth/issue34/repro_sgn.vhdl
new file mode 100644
index 000000000..fa23693d3
--- /dev/null
+++ b/testsuite/synth/issue34/repro_sgn.vhdl
@@ -0,0 +1,44 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity sub_sgn is
+  port (
+    clk : in std_logic;
+    a : in signed(7 downto 0);
+    b : out signed(7 downto 0)
+  );
+end sub_sgn;
+
+architecture rtl of sub_sgn is
+begin
+  process(clk)
+  begin
+    if rising_edge(clk) then
+      b <= a;
+    end if;
+  end process;
+end rtl;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity repro_sgn is
+  port (
+    clk : in std_logic;
+    a : in signed(7 downto 0);
+    b : out signed(7 downto 0)
+  );
+end repro_sgn;
+
+architecture rtl of repro_sgn is
+begin
+  i_sub_sgn : entity work.sub_sgn
+  port map (
+    clk => clk,
+    a => a,
+    b => b
+  );
+end rtl;
diff --git a/testsuite/synth/issue34/repro_slv.vhdl b/testsuite/synth/issue34/repro_slv.vhdl
new file mode 100644
index 000000000..4b0e1b0e5
--- /dev/null
+++ b/testsuite/synth/issue34/repro_slv.vhdl
@@ -0,0 +1,42 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity sub_slv is
+  port (
+    clk : in std_logic;
+    a : in std_logic_vector(7 downto 0);
+    b : out std_logic_vector(7 downto 0)
+  );
+end sub_slv;
+
+architecture rtl of sub_slv is
+begin
+  process(clk)
+  begin
+    if rising_edge(clk) then
+      b <= a;
+    end if;
+  end process;
+end rtl;
+
+
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity repro_slv is
+  port (
+    clk : in std_logic;
+    a : in std_logic_vector(7 downto 0);
+    b : out std_logic_vector(7 downto 0)
+  );
+end repro_slv;
+
+architecture rtl of repro_slv is
+begin
+  i_sub_slv : entity work.sub_slv
+  port map (
+    clk => clk,
+    a => a,
+    b => b
+  );
+end rtl;
diff --git a/testsuite/synth/issue34/repro_uns.vhdl b/testsuite/synth/issue34/repro_uns.vhdl
new file mode 100644
index 000000000..d0641d509
--- /dev/null
+++ b/testsuite/synth/issue34/repro_uns.vhdl
@@ -0,0 +1,44 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity sub_uns is
+  port (
+    clk : in std_logic;
+    a : in unsigned(7 downto 0);
+    b : out unsigned(7 downto 0)
+  );
+end sub_uns;
+
+architecture rtl of sub_uns is
+begin
+  process(clk)
+  begin
+    if rising_edge(clk) then
+      b <= a;
+    end if;
+  end process;
+end rtl;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity repro_uns is
+  port (
+    clk : in std_logic;
+    a : in unsigned(7 downto 0);
+    b : out unsigned(7 downto 0)
+  );
+end repro_uns;
+
+architecture rtl of repro_uns is
+begin
+  i_sub_uns : entity work.sub_uns
+  port map (
+    clk => clk,
+    a => a,
+    b => b
+  );
+end rtl;
diff --git a/testsuite/synth/issue34/submodule.vhdl b/testsuite/synth/issue34/submodule.vhdl
new file mode 100644
index 000000000..bc282985a
--- /dev/null
+++ b/testsuite/synth/issue34/submodule.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity submodule is
+  port (
+    clk : in std_logic;
+    a : in std_logic_vector(7 downto 0);
+    b : out std_logic_vector(7 downto 0)
+  );
+end submodule;
+
+architecture rtl of submodule is
+begin
+  process(clk)
+  begin
+    if rising_edge(clk) then
+      b <= a;
+    end if;
+  end process;
+end rtl;
diff --git a/testsuite/synth/issue34/tb_repro_nat.vhdl b/testsuite/synth/issue34/tb_repro_nat.vhdl
new file mode 100644
index 000000000..acfe72fea
--- /dev/null
+++ b/testsuite/synth/issue34/tb_repro_nat.vhdl
@@ -0,0 +1,34 @@
+entity tb_repro_nat is
+end tb_repro_nat;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_repro_nat is
+  signal clk : std_logic;
+  signal a : natural;
+  signal b : natural;
+begin
+  dut: entity work.repro_nat
+    port map (
+      clk => clk, a => a, b => b);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    a <= 125;
+    pulse;
+    assert b = 125 severity failure;
+
+    a <= 7689;
+    pulse;
+    assert b = 7689 severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue34/tb_repro_rng1.vhdl b/testsuite/synth/issue34/tb_repro_rng1.vhdl
new file mode 100644
index 000000000..09f385a58
--- /dev/null
+++ b/testsuite/synth/issue34/tb_repro_rng1.vhdl
@@ -0,0 +1,34 @@
+entity tb_repro_rng1 is
+end tb_repro_rng1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_repro_rng1 is
+  signal clk : std_logic;
+  signal a : natural range 0 to 7;
+  signal b : natural range 0 to 7;
+begin
+  dut: entity work.repro_rng1
+    port map (
+      clk => clk, a => a, b => b);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    a <= 1;
+    pulse;
+    assert b = 1 severity failure;
+
+    a <= 6;
+    pulse;
+    assert b = 6 severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue34/tb_repro_sgn.vhdl b/testsuite/synth/issue34/tb_repro_sgn.vhdl
new file mode 100644
index 000000000..3961e6702
--- /dev/null
+++ b/testsuite/synth/issue34/tb_repro_sgn.vhdl
@@ -0,0 +1,35 @@
+entity tb_repro_sgn is
+end tb_repro_sgn;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_repro_sgn is
+  signal clk : std_logic;
+  signal a : signed(7 downto 0);
+  signal b : signed(7 downto 0);
+begin
+  dut: entity work.repro_sgn
+    port map (
+      clk => clk, a => a, b => b);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    a <= x"ab";
+    pulse;
+    assert b = x"ab" severity failure;
+
+    a <= x"12";
+    pulse;
+    assert b = x"12" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue34/tb_repro_slv.vhdl b/testsuite/synth/issue34/tb_repro_slv.vhdl
new file mode 100644
index 000000000..45f0621eb
--- /dev/null
+++ b/testsuite/synth/issue34/tb_repro_slv.vhdl
@@ -0,0 +1,34 @@
+entity tb_repro_slv is
+end tb_repro_slv;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_repro_slv is
+  signal clk : std_logic;
+  signal a : std_logic_vector(7 downto 0);
+  signal b : std_logic_vector(7 downto 0);
+begin
+  dut: entity work.repro_slv
+    port map (
+      clk => clk, a => a, b => b);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    a <= x"ab";
+    pulse;
+    assert b = x"ab" severity failure;
+
+    a <= x"12";
+    pulse;
+    assert b = x"12" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue34/tb_repro_uns.vhdl b/testsuite/synth/issue34/tb_repro_uns.vhdl
new file mode 100644
index 000000000..a54a636eb
--- /dev/null
+++ b/testsuite/synth/issue34/tb_repro_uns.vhdl
@@ -0,0 +1,35 @@
+entity tb_repro_uns is
+end tb_repro_uns;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_repro_uns is
+  signal clk : std_logic;
+  signal a : unsigned(7 downto 0);
+  signal b : unsigned(7 downto 0);
+begin
+  dut: entity work.repro_uns
+    port map (
+      clk => clk, a => a, b => b);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    a <= x"ab";
+    pulse;
+    assert b = x"ab" severity failure;
+
+    a <= x"12";
+    pulse;
+    assert b = x"12" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue34/testsuite.sh b/testsuite/synth/issue34/testsuite.sh
new file mode 100755
index 000000000..82088c6d8
--- /dev/null
+++ b/testsuite/synth/issue34/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in repro_slv repro_uns repro_sgn repro_nat repro_rng1; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+done
+
+echo "Test successful"