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author | Tristan Gingold <tgingold@free.fr> | 2015-01-22 05:09:37 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2015-01-22 05:09:37 +0100 |
commit | e18db47d92bb735f782e4409abb77d7b9233672f (patch) | |
tree | c17431465d3840ce1d3bb0588987f8ca66a8de38 /testsuite | |
parent | 34e81c81b0a32d0974617672f2087fceeaba80a0 (diff) | |
download | ghdl-e18db47d92bb735f782e4409abb77d7b9233672f.tar.gz ghdl-e18db47d92bb735f782e4409abb77d7b9233672f.tar.bz2 ghdl-e18db47d92bb735f782e4409abb77d7b9233672f.zip |
Add bug09 testcase on time<->univ_integer conversions.
Diffstat (limited to 'testsuite')
-rwxr-xr-x | testsuite/gna/bug09/testsuite.sh | 13 | ||||
-rw-r--r-- | testsuite/gna/bug09/univ1.vhdl | 22 | ||||
-rw-r--r-- | testsuite/gna/bug09/univ2.vhdl | 17 |
3 files changed, 52 insertions, 0 deletions
diff --git a/testsuite/gna/bug09/testsuite.sh b/testsuite/gna/bug09/testsuite.sh new file mode 100755 index 000000000..8d98967e6 --- /dev/null +++ b/testsuite/gna/bug09/testsuite.sh @@ -0,0 +1,13 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze univ1.vhdl +elab_simulate_failure univ1 + +analyze univ2.vhdl +elab_simulate univ2 + +clean + +echo "Test successful" diff --git a/testsuite/gna/bug09/univ1.vhdl b/testsuite/gna/bug09/univ1.vhdl new file mode 100644 index 000000000..dfdc1f80f --- /dev/null +++ b/testsuite/gna/bug09/univ1.vhdl @@ -0,0 +1,22 @@ +entity univ1 is +end entity; + +architecture foo of univ1 is + signal i: integer := Time'POS(Time'High); -- should produce error + + -- 6.4.2.3 Signal declarations, para 5, first sentence: + -- If the signal declaration includes the assignment symbol followed by an + -- expression, it shall be of the same type as the signal. Such an + -- expression is said to be a default expression. + -- + -- -1993 4.3.1.2 Signal declarations, para 6, first sentence: + -- If the signal declaration includes the assignment symbol followed by + -- an expression, it must be of the same type as the signal. + + -- 'POS returns universal integer + -- +begin + assert False + report "i = " & integer'IMAGE(i) -- shows left clipping instead of error + severity ERROR; +end architecture;
\ No newline at end of file diff --git a/testsuite/gna/bug09/univ2.vhdl b/testsuite/gna/bug09/univ2.vhdl new file mode 100644 index 000000000..af19d38e3 --- /dev/null +++ b/testsuite/gna/bug09/univ2.vhdl @@ -0,0 +1,17 @@ + +entity univ2 is +end entity; + +architecture foo of univ2 is + +begin + assert False + report "Time'HIGH = " & Time'IMAGE(Time'VAL(Time'POS(Time'HIGH))) + severity NOTE; + assert False + report "should produce 9223372036854775807" + severity NOTE; +end architecture; + +-- 'POS returns universal integer +-- 'VAL parameter is any integer type (including universal integer)
\ No newline at end of file |