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authorTristan Gingold <tgingold@free.fr>2016-05-31 06:46:37 +0200
committerTristan Gingold <tgingold@free.fr>2016-05-31 08:06:49 +0200
commitdfcb6a20351cf7e7150fbcdd4c35dd21132d81ea (patch)
treeae5d225956539af5b04d1b7acc02578802f69080 /testsuite
parentaf9d1d913a1fc586afd39b87bed6f4c78d171a9b (diff)
downloadghdl-dfcb6a20351cf7e7150fbcdd4c35dd21132d81ea.tar.gz
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vhdl2008: implement new 'use clause' rules for types.
Adjust test issue72.
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/gna/bug04/std_logic_warning.vhdl8
-rw-r--r--testsuite/gna/issue72/fixed.vhdl2
-rwxr-xr-xtestsuite/gna/issue72/testsuite.sh8
3 files changed, 9 insertions, 9 deletions
diff --git a/testsuite/gna/bug04/std_logic_warning.vhdl b/testsuite/gna/bug04/std_logic_warning.vhdl
index a71b2dd04..cbe731601 100644
--- a/testsuite/gna/bug04/std_logic_warning.vhdl
+++ b/testsuite/gna/bug04/std_logic_warning.vhdl
@@ -41,13 +41,13 @@ UNLABELLED:
process
begin
wait for 1 ns;
- a <= 'X';
+ a <= ieee.std_logic_1164.'X';
wait for 1 ns;
- b <= '1';
+ b <= ieee.std_logic_1164.'1';
wait for 1 ns;
- a <= '0';
+ a <= ieee.std_logic_1164.'0';
wait for 1 ns;
- b <= '0';
+ b <= ieee.std_logic_1164.'0';
wait;
end process;
diff --git a/testsuite/gna/issue72/fixed.vhdl b/testsuite/gna/issue72/fixed.vhdl
index 214c6049a..8b13577ff 100644
--- a/testsuite/gna/issue72/fixed.vhdl
+++ b/testsuite/gna/issue72/fixed.vhdl
@@ -22,7 +22,7 @@ begin -- architecture rtl
process (clk) is
begin -- process
if clk'event and clk = '1' then -- rising clock edge
- if input = one then
+ if input = work.issue_pkg.one then
output <= '1';
else
output <= '0';
diff --git a/testsuite/gna/issue72/testsuite.sh b/testsuite/gna/issue72/testsuite.sh
index 309a6b47d..1119937bb 100755
--- a/testsuite/gna/issue72/testsuite.sh
+++ b/testsuite/gna/issue72/testsuite.sh
@@ -8,9 +8,9 @@ analyze fixed.vhdl
clean
-#GHDL_STD_FLAGS=--std=08
-#analyze issue_pkg.vhdl
-#analyze issue.vhdl
-#clean
+GHDL_STD_FLAGS=--std=08
+analyze issue_pkg.vhdl
+analyze issue.vhdl
+clean
echo "Test successful"