testsuite/synth: add tests for dyn_extract expand.

6 files changed, 245 insertions, 0 deletions

diff --git a/testsuite/synth/memmux01/memmux01.vhdl b/testsuite/synth/memmux01/memmux01.vhdl
new file mode 100644
index 000000000..27d0169e9
--- /dev/null
+++ b/testsuite/synth/memmux01/memmux01.vhdl
@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity memmux01 is
+  port (
+    wen : std_logic;
+    addr : std_logic_vector (3 downto 0);
+    wdat : std_logic;
+    rdat : out std_logic_vector (15 downto 0);
+    clk : std_logic;
+    rst : std_logic);
+end memmux01;
+
+architecture rtl of memmux01 is
+begin
+  process (clk)
+  is
+    variable mem : std_logic_vector (15 downto 0);
+    variable ad : natural range 0 to 15;
+  begin
+    if rising_edge(clk) then
+      rdat <= mem;
+
+      if rst = '1' then
+        mem := (others => '0');
+      else
+        ad := to_integer(unsigned(addr));
+        if wen = '1' then
+          mem (ad) := wdat;
+        end if;
+      end if;
+    end if;
+  end process;
+end rtl;
diff --git a/testsuite/synth/memmux01/memmux02.vhdl b/testsuite/synth/memmux01/memmux02.vhdl
new file mode 100644
index 000000000..eee49c7bb
--- /dev/null
+++ b/testsuite/synth/memmux01/memmux02.vhdl
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity memmux02 is
+  port (
+    wen : std_logic;
+    addr : std_logic_vector (3 downto 0);
+    rdat : out std_logic;
+    wdat : std_logic_vector (15 downto 0);
+    clk : std_logic;
+    rst : std_logic);
+end memmux02;
+
+architecture rtl of memmux02 is
+begin
+  process (clk)
+  is
+    variable mem : std_logic_vector (15 downto 0);
+    variable ad : natural range 0 to 15;
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        mem := (others => '0');
+      else
+        ad := to_integer(unsigned(addr));
+        rdat <= mem (ad);
+        if wen = '1' then
+          mem := wdat;
+        end if;
+      end if;
+    end if;
+  end process;
+end rtl;
diff --git a/testsuite/synth/memmux01/memmux03.vhdl b/testsuite/synth/memmux01/memmux03.vhdl
new file mode 100644
index 000000000..81c54d0c4
--- /dev/null
+++ b/testsuite/synth/memmux01/memmux03.vhdl
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity memmux03 is
+  port (
+    wen : std_logic;
+    addr : std_logic_vector (3 downto 0);
+    rdat : out std_logic;
+    wdat : std_logic_vector (12 downto 0);
+    clk : std_logic;
+    rst : std_logic);
+end memmux03;
+
+architecture rtl of memmux03 is
+begin
+  process (clk)
+  is
+    variable mem : std_logic_vector (12 downto 0);
+    variable ad : natural range 0 to 12;
+  begin
+    if rising_edge(clk) then
+      if rst = '1' then
+        mem := (others => '0');
+      else
+        ad := to_integer(unsigned(addr));
+        rdat <= mem (ad);
+        if wen = '1' then
+          mem := wdat;
+        end if;
+      end if;
+    end if;
+  end process;
+end rtl;
diff --git a/testsuite/synth/memmux01/tb_memmux02.vhdl b/testsuite/synth/memmux01/tb_memmux02.vhdl
new file mode 100644
index 000000000..b4bfbd7b4
--- /dev/null
+++ b/testsuite/synth/memmux01/tb_memmux02.vhdl
@@ -0,0 +1,63 @@
+entity tb_memmux02 is
+end tb_memmux02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_memmux02 is
+  signal wen  : std_logic;
+  signal addr : std_logic_vector (3 downto 0);
+  signal rdat : std_logic;
+  signal wdat : std_logic_vector (15 downto 0);
+  signal clk  : std_logic;
+  signal rst  : std_logic;
+begin
+  dut : entity work.memmux02
+    port map (
+      wen  => wen,
+      addr => addr,
+      rdat => rdat,
+      wdat => wdat,
+      clk  => clk,
+      rst  => rst);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+
+    constant c : std_logic_vector (15 downto 0) := x"56bc";
+  begin
+    rst <= '1';
+    wen <= '0';
+    wdat <= c;
+    addr <= x"0";
+    pulse;
+
+    rst <= '0';
+    pulse;
+    assert rdat = '0' severity failure;
+
+    addr <= x"4";
+    wen <= '1';
+    pulse;
+    assert rdat = '0' severity failure;
+
+    wen <= '0';
+    pulse;
+    assert rdat = '1' severity failure;
+
+    for i in c'range loop
+      addr <= std_logic_vector (to_unsigned (i, 4));
+      pulse;
+      assert rdat = c(i) severity failure;
+    end loop;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/memmux01/tb_memmux03.vhdl b/testsuite/synth/memmux01/tb_memmux03.vhdl
new file mode 100644
index 000000000..39477acd6
--- /dev/null
+++ b/testsuite/synth/memmux01/tb_memmux03.vhdl
@@ -0,0 +1,63 @@
+entity tb_memmux03 is
+end tb_memmux03;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_memmux03 is
+  signal wen  : std_logic;
+  signal addr : std_logic_vector (3 downto 0);
+  signal rdat : std_logic;
+  signal wdat : std_logic_vector (12 downto 0);
+  signal clk  : std_logic;
+  signal rst  : std_logic;
+begin
+  dut : entity work.memmux03
+    port map (
+      wen  => wen,
+      addr => addr,
+      rdat => rdat,
+      wdat => wdat,
+      clk  => clk,
+      rst  => rst);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+
+    constant c : std_logic_vector (12 downto 0) := b"1_0101_1100_1001";
+  begin
+    rst <= '1';
+    wen <= '0';
+    wdat <= c;
+    addr <= x"0";
+    pulse;
+
+    rst <= '0';
+    pulse;
+    assert rdat = '0' severity failure;
+
+    addr <= x"3";
+    wen <= '1';
+    pulse;
+    assert rdat = '0' severity failure;
+
+    wen <= '0';
+    pulse;
+    assert rdat = '1' severity failure;
+
+    for i in c'range loop
+      addr <= std_logic_vector (to_unsigned (i, 4));
+      pulse;
+      assert rdat = c(i) severity failure;
+    end loop;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/memmux01/testsuite.sh b/testsuite/synth/memmux01/testsuite.sh
new file mode 100755
index 000000000..d3ba44953
--- /dev/null
+++ b/testsuite/synth/memmux01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in memmux02 memmux03; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"