testsuite/synth: add tests for std_logic_arith

17 files changed, 1055 insertions, 0 deletions

diff --git a/testsuite/synth/sns01/adds.vhdl b/testsuite/synth/sns01/adds.vhdl
new file mode 100644
index 000000000..0347f7cf5
--- /dev/null
+++ b/testsuite/synth/sns01/adds.vhdl
@@ -0,0 +1,68 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity adds is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    add_u4u3u : out std_logic_vector (3 downto 0);
+    add_s4s3s : out std_logic_vector (3 downto 0);
+    add_u4s3s : out std_logic_vector (4 downto 0);
+    add_s4u3s : out std_logic_vector (3 downto 0);
+    add_u4iu  : out std_logic_vector (3 downto 0);
+    add_iu3u  : out std_logic_vector (2 downto 0);
+    add_s4is  : out std_logic_vector (3 downto 0);
+    add_is3s  : out std_logic_vector (2 downto 0);
+    add_u4lu  : out std_logic_vector (3 downto 0);
+    add_lu3u  : out std_logic_vector (2 downto 0);
+    add_s4ls  : out std_logic_vector (3 downto 0);
+    add_ls3s  : out std_logic_vector (2 downto 0);
+
+    add_u4u3v : out std_logic_vector (3 downto 0);
+    add_s4s3v : out std_logic_vector (3 downto 0);
+    add_u4s3v : out std_logic_vector (4 downto 0);
+    add_s4u3v : out std_logic_vector (3 downto 0);
+    add_u4iv  : out std_logic_vector (3 downto 0);
+    add_iu3v  : out std_logic_vector (2 downto 0);
+    add_s4iv  : out std_logic_vector (3 downto 0);
+    add_is3v  : out std_logic_vector (2 downto 0);
+    add_u4lv  : out std_logic_vector (3 downto 0);
+    add_lu3v  : out std_logic_vector (2 downto 0);
+    add_s4lv  : out std_logic_vector (3 downto 0);
+    add_ls3v  : out std_logic_vector (2 downto 0));
+end adds;
+
+library ieee;
+use ieee.std_logic_arith.all;
+
+architecture behav of adds is
+begin
+  add_u4u3u <= std_logic_vector (unsigned'(unsigned(l4) + unsigned(r3)));
+  add_s4s3s <= std_logic_vector (signed'(signed(l4) + signed(r3)));
+  add_u4s3s <= std_logic_vector (signed'(unsigned(l4) + signed(r3)));
+  add_s4u3s <= std_logic_vector (signed'(signed(l4) + unsigned(r3)));
+  add_u4iu  <= std_logic_vector (unsigned'(unsigned(l4) + ri));
+  add_iu3u  <= std_logic_vector (unsigned'(li + unsigned(r3)));
+  add_s4is  <= std_logic_vector (signed'(signed(l4) + ri));
+  add_is3s  <= std_logic_vector (signed'(li + signed(r3)));
+  add_u4lu  <= std_logic_vector (unsigned'(unsigned(l4) + r3(0)));
+  add_lu3u  <= std_logic_vector (unsigned'(l4(0) + unsigned(r3)));
+  add_s4ls  <= std_logic_vector (signed'(signed(l4) + r3(0)));
+  add_ls3s  <= std_logic_vector (signed'(l4(0) + signed(r3)));
+
+  add_u4u3v <= unsigned(l4) + unsigned(r3);
+  add_s4s3v <= signed(l4) + signed(r3);
+  add_u4s3v <= unsigned(l4) + signed(r3);
+  add_s4u3v <= signed(l4) + unsigned(r3);
+  add_u4iv  <= unsigned(l4) + ri;
+  add_iu3v  <= li + unsigned(r3);
+  add_s4iv  <= signed(l4) + ri;
+  add_is3v  <= li + signed(r3);
+  add_u4lv  <= unsigned(l4) + r3(0);
+  add_lu3v  <= l4(0) + unsigned(r3);
+  add_s4lv  <= signed(l4) + r3(0);
+  add_ls3v  <= l4(0) + signed(r3);
+end behav;
diff --git a/testsuite/synth/sns01/cmpeq.vhdl b/testsuite/synth/sns01/cmpeq.vhdl
new file mode 100644
index 000000000..d9554022e
--- /dev/null
+++ b/testsuite/synth/sns01/cmpeq.vhdl
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmpeq is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    eq_u4u3 : out boolean;
+    eq_s4s3 : out boolean;
+    eq_u4s3 : out boolean;
+    eq_s4u3 : out boolean;
+    eq_u4i  : out boolean;
+    eq_iu3  : out boolean;
+    eq_s4i  : out boolean;
+    eq_is3  : out boolean);
+end cmpeq;
+
+library ieee;
+use ieee.std_logic_arith.all;
+
+architecture behav of cmpeq is
+begin
+  eq_u4u3 <= unsigned(l4) = unsigned(r3);
+  eq_s4s3 <= signed(l4) = signed(r3);
+  eq_u4s3 <= unsigned(l4) = signed(r3);
+  eq_s4u3 <= signed(l4) = unsigned(r3);
+  eq_u4i  <= unsigned(l4) = ri;
+  eq_iu3  <= li = unsigned(r3);
+  eq_s4i  <= signed(l4) = ri;
+  eq_is3  <= li = signed(r3);
+end behav;
diff --git a/testsuite/synth/sns01/cmpge.vhdl b/testsuite/synth/sns01/cmpge.vhdl
new file mode 100644
index 000000000..652c81bd5
--- /dev/null
+++ b/testsuite/synth/sns01/cmpge.vhdl
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmpge is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    ge_u4u3 : out boolean;
+    ge_s4s3 : out boolean;
+    ge_u4s3 : out boolean;
+    ge_s4u3 : out boolean;
+    ge_u4i  : out boolean;
+    ge_iu3  : out boolean;
+    ge_s4i  : out boolean;
+    ge_is3  : out boolean);
+end cmpge;
+
+library ieee;
+use ieee.std_logic_arith.all;
+
+architecture behav of cmpge is
+begin
+  ge_u4u3 <= unsigned(l4) >= unsigned(r3);
+  ge_s4s3 <= signed(l4) >= signed(r3);
+  ge_u4s3 <= unsigned(l4) >= signed(r3);
+  ge_s4u3 <= signed(l4) >= unsigned(r3);
+  ge_u4i  <= unsigned(l4) >= ri;
+  ge_iu3  <= li >= unsigned(r3);
+  ge_s4i  <= signed(l4) >= ri;
+  ge_is3  <= li >= signed(r3);
+end behav;
diff --git a/testsuite/synth/sns01/cmpgt.vhdl b/testsuite/synth/sns01/cmpgt.vhdl
new file mode 100644
index 000000000..4f72b0682
--- /dev/null
+++ b/testsuite/synth/sns01/cmpgt.vhdl
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmpgt is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    gt_u4u3 : out boolean;
+    gt_s4s3 : out boolean;
+    gt_u4s3 : out boolean;
+    gt_s4u3 : out boolean;
+    gt_u4i  : out boolean;
+    gt_iu3  : out boolean;
+    gt_s4i  : out boolean;
+    gt_is3  : out boolean);
+end cmpgt;
+
+library ieee;
+use ieee.std_logic_arith.all;
+
+architecture behav of cmpgt is
+begin
+  gt_u4u3 <= unsigned(l4) > unsigned(r3);
+  gt_s4s3 <= signed(l4) > signed(r3);
+  gt_u4s3 <= unsigned(l4) > signed(r3);
+  gt_s4u3 <= signed(l4) > unsigned(r3);
+  gt_u4i  <= unsigned(l4) > ri;
+  gt_iu3  <= li > unsigned(r3);
+  gt_s4i  <= signed(l4) > ri;
+  gt_is3  <= li > signed(r3);
+end behav;
diff --git a/testsuite/synth/sns01/cmple.vhdl b/testsuite/synth/sns01/cmple.vhdl
new file mode 100644
index 000000000..f5397fb82
--- /dev/null
+++ b/testsuite/synth/sns01/cmple.vhdl
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmple is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    le_u4u3 : out boolean;
+    le_s4s3 : out boolean;
+    le_u4s3 : out boolean;
+    le_s4u3 : out boolean;
+    le_u4i  : out boolean;
+    le_iu3  : out boolean;
+    le_s4i  : out boolean;
+    le_is3  : out boolean);
+end cmple;
+
+library ieee;
+use ieee.std_logic_arith.all;
+
+architecture behav of cmple is
+begin
+  le_u4u3 <= unsigned(l4) <= unsigned(r3);
+  le_s4s3 <= signed(l4) <= signed(r3);
+  le_u4s3 <= unsigned(l4) <= signed(r3);
+  le_s4u3 <= signed(l4) <= unsigned(r3);
+  le_u4i  <= unsigned(l4) <= ri;
+  le_iu3  <= li <= unsigned(r3);
+  le_s4i  <= signed(l4) <= ri;
+  le_is3  <= li <= signed(r3);
+end behav;
diff --git a/testsuite/synth/sns01/cmplt.vhdl b/testsuite/synth/sns01/cmplt.vhdl
new file mode 100644
index 000000000..bc124128f
--- /dev/null
+++ b/testsuite/synth/sns01/cmplt.vhdl
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmplt is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    lt_u4u3 : out boolean;
+    lt_s4s3 : out boolean;
+    lt_u4s3 : out boolean;
+    lt_s4u3 : out boolean;
+    lt_u4i  : out boolean;
+    lt_iu3  : out boolean;
+    lt_s4i  : out boolean;
+    lt_is3  : out boolean);
+end cmplt;
+
+library ieee;
+use ieee.std_logic_arith.all;
+
+architecture behav of cmplt is
+begin
+  lt_u4u3 <= unsigned(l4) < unsigned(r3);
+  lt_s4s3 <= signed(l4) < signed(r3);
+  lt_u4s3 <= unsigned(l4) < signed(r3);
+  lt_s4u3 <= signed(l4) < unsigned(r3);
+  lt_u4i  <= unsigned(l4) < ri;
+  lt_iu3  <= li < unsigned(r3);
+  lt_s4i  <= signed(l4) < ri;
+  lt_is3  <= li < signed(r3);
+end behav;
diff --git a/testsuite/synth/sns01/cmpne.vhdl b/testsuite/synth/sns01/cmpne.vhdl
new file mode 100644
index 000000000..051594d8e
--- /dev/null
+++ b/testsuite/synth/sns01/cmpne.vhdl
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmpne is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    ne_u4u3 : out boolean;
+    ne_s4s3 : out boolean;
+    ne_u4s3 : out boolean;
+    ne_s4u3 : out boolean;
+    ne_u4i  : out boolean;
+    ne_iu3  : out boolean;
+    ne_s4i  : out boolean;
+    ne_is3  : out boolean);
+end cmpne;
+
+library ieee;
+use ieee.std_logic_arith.all;
+
+architecture behav of cmpne is
+begin
+  ne_u4u3 <= unsigned(l4) /= unsigned(r3);
+  ne_s4s3 <= signed(l4) /= signed(r3);
+  ne_u4s3 <= unsigned(l4) /= signed(r3);
+  ne_s4u3 <= signed(l4) /= unsigned(r3);
+  ne_u4i  <= unsigned(l4) /= ri;
+  ne_iu3  <= li /= unsigned(r3);
+  ne_s4i  <= signed(l4) /= ri;
+  ne_is3  <= li /= signed(r3);
+end behav;
diff --git a/testsuite/synth/sns01/subs.vhdl b/testsuite/synth/sns01/subs.vhdl
new file mode 100644
index 000000000..26f1dec14
--- /dev/null
+++ b/testsuite/synth/sns01/subs.vhdl
@@ -0,0 +1,68 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity subs is
+  port (
+    li : integer;
+    ri : integer;
+    l4 : std_logic_vector (3 downto 0);
+    r3 : std_logic_vector (2 downto 0);
+
+    sub_u4u3u : out std_logic_vector (3 downto 0);
+    sub_s4s3s : out std_logic_vector (3 downto 0);
+    sub_u4s3s : out std_logic_vector (4 downto 0);
+    sub_s4u3s : out std_logic_vector (3 downto 0);
+    sub_u4iu  : out std_logic_vector (3 downto 0);
+    sub_iu3u  : out std_logic_vector (2 downto 0);
+    sub_s4is  : out std_logic_vector (3 downto 0);
+    sub_is3s  : out std_logic_vector (2 downto 0);
+    sub_u4lu  : out std_logic_vector (3 downto 0);
+    sub_lu3u  : out std_logic_vector (2 downto 0);
+    sub_s4ls  : out std_logic_vector (3 downto 0);
+    sub_ls3s  : out std_logic_vector (2 downto 0);
+
+    sub_u4u3v : out std_logic_vector (3 downto 0);
+    sub_s4s3v : out std_logic_vector (3 downto 0);
+    sub_u4s3v : out std_logic_vector (4 downto 0);
+    sub_s4u3v : out std_logic_vector (3 downto 0);
+    sub_u4iv  : out std_logic_vector (3 downto 0);
+    sub_iu3v  : out std_logic_vector (2 downto 0);
+    sub_s4iv  : out std_logic_vector (3 downto 0);
+    sub_is3v  : out std_logic_vector (2 downto 0);
+    sub_u4lv  : out std_logic_vector (3 downto 0);
+    sub_lu3v  : out std_logic_vector (2 downto 0);
+    sub_s4lv  : out std_logic_vector (3 downto 0);
+    sub_ls3v  : out std_logic_vector (2 downto 0));
+end subs;
+
+library ieee;
+use ieee.std_logic_arith.all;
+
+architecture behav of subs is
+begin
+  sub_u4u3u <= std_logic_vector (unsigned'(unsigned(l4) - unsigned(r3)));
+  sub_s4s3s <= std_logic_vector (signed'(signed(l4) - signed(r3)));
+  sub_u4s3s <= std_logic_vector (signed'(unsigned(l4) - signed(r3)));
+  sub_s4u3s <= std_logic_vector (signed'(signed(l4) - unsigned(r3)));
+  sub_u4iu  <= std_logic_vector (unsigned'(unsigned(l4) - ri));
+  sub_iu3u  <= std_logic_vector (unsigned'(li - unsigned(r3)));
+  sub_s4is  <= std_logic_vector (signed'(signed(l4) - ri));
+  sub_is3s  <= std_logic_vector (signed'(li - signed(r3)));
+  sub_u4lu  <= std_logic_vector (unsigned'(unsigned(l4) - r3(0)));
+  sub_lu3u  <= std_logic_vector (unsigned'(l4(0) - unsigned(r3)));
+  sub_s4ls  <= std_logic_vector (signed'(signed(l4) - r3(0)));
+  sub_ls3s  <= std_logic_vector (signed'(l4(0) - signed(r3)));
+
+  sub_u4u3v <= unsigned(l4) - unsigned(r3);
+  sub_s4s3v <= signed(l4) - signed(r3);
+  sub_u4s3v <= unsigned(l4) - signed(r3);
+  sub_s4u3v <= signed(l4) - unsigned(r3);
+  sub_u4iv  <= unsigned(l4) - ri;
+  sub_iu3v  <= li - unsigned(r3);
+  sub_s4iv  <= signed(l4) - ri;
+  sub_is3v  <= li - signed(r3);
+  sub_u4lv  <= unsigned(l4) - r3(0);
+  sub_lu3v  <= l4(0) - unsigned(r3);
+  sub_s4lv  <= signed(l4) - r3(0);
+  sub_ls3v  <= l4(0) - signed(r3);
+end behav;
diff --git a/testsuite/synth/sns01/tb_adds.vhdl b/testsuite/synth/sns01/tb_adds.vhdl
new file mode 100644
index 000000000..936559c8d
--- /dev/null
+++ b/testsuite/synth/sns01/tb_adds.vhdl
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_adds is
+end;
+
+architecture behav of tb_adds is
+  type sl_map_type is array (std_ulogic) of character;
+  constant sl_map : sl_map_type := "UX01ZWLH-";
+
+  function to_string(v : std_logic_vector) return string
+  is
+    alias av : std_logic_vector(1 to v'length) is v;
+    variable res : string (1 to v'length);
+  begin
+    for i in res'range loop
+      res (i) := sl_map (av (i));
+    end loop;
+    return res;
+  end to_string;
+
+  signal li : integer := 0;
+  signal ri : integer := 0;
+  signal l4 : std_logic_vector (3 downto 0) := "0000";
+  signal r3 : std_logic_vector (2 downto 0) := "000";
+  signal add_u4u3u : std_logic_vector (3 downto 0) := "0000";
+  signal add_s4s3s : std_logic_vector (3 downto 0) := "0000";
+  signal add_u4s3s : std_logic_vector (4 downto 0) := "00000";
+  signal add_s4u3s : std_logic_vector (3 downto 0) := "0000";
+  signal add_u4iu : std_logic_vector (3 downto 0) := "0000";
+  signal add_iu3u : std_logic_vector (2 downto 0) := "000";
+  signal add_s4is : std_logic_vector (3 downto 0) := "0000";
+  signal add_is3s : std_logic_vector (2 downto 0) := "000";
+  signal add_u4lu : std_logic_vector (3 downto 0) := "0000";
+  signal add_lu3u : std_logic_vector (2 downto 0) := "000";
+  signal add_s4ls : std_logic_vector (3 downto 0) := "0000";
+  signal add_ls3s : std_logic_vector (2 downto 0) := "000";
+
+  signal add_u4u3v : std_logic_vector (3 downto 0) := "0000";
+  signal add_s4s3v : std_logic_vector (3 downto 0) := "0000";
+  signal add_u4s3v : std_logic_vector (4 downto 0) := "00000";
+  signal add_s4u3v : std_logic_vector (3 downto 0) := "0000";
+  signal add_u4iv : std_logic_vector (3 downto 0) := "0000";
+  signal add_iu3v : std_logic_vector (2 downto 0) := "000";
+  signal add_s4iv : std_logic_vector (3 downto 0) := "0000";
+  signal add_is3v : std_logic_vector (2 downto 0) := "000";
+  signal add_u4lv : std_logic_vector (3 downto 0) := "0000";
+  signal add_lu3v : std_logic_vector (2 downto 0) := "000";
+  signal add_s4lv : std_logic_vector (3 downto 0) := "0000";
+  signal add_ls3v : std_logic_vector (2 downto 0) := "000";
+begin
+
+  dut: entity work.adds
+    port map (
+      l4 => l4,
+      r3 => r3,
+      li => li,
+      ri => ri,
+      add_u4u3u => add_u4u3u,
+      add_s4s3s => add_s4s3s,
+      add_u4s3s => add_u4s3s,
+      add_s4u3s => add_s4u3s,
+      add_u4iu => add_u4iu,
+      add_iu3u => add_iu3u,
+      add_s4is => add_s4is,
+      add_is3s => add_is3s,
+      add_u4lu => add_u4lu,
+      add_lu3u => add_lu3u,
+      add_s4ls => add_s4ls,
+      add_ls3s => add_ls3s,
+
+      add_u4u3v => add_u4u3v,
+      add_s4s3v => add_s4s3v,
+      add_u4s3v => add_u4s3v,
+      add_s4u3v => add_s4u3v,
+      add_u4iv => add_u4iv,
+      add_iu3v => add_iu3v,
+      add_s4iv => add_s4iv,
+      add_is3v => add_is3v,
+      add_u4lv => add_u4lv,
+      add_lu3v => add_lu3v,
+      add_s4lv => add_s4lv,
+      add_ls3v => add_ls3v);
+
+  process
+  begin
+    for i in -8 to 7 loop
+      li <= i;
+      l4 <= conv_std_logic_vector (i, 4);
+      for j in -4 to 3 loop
+        r3 <= conv_std_logic_vector (j, 3);
+        ri <= j;
+        wait for 1 ns;
+        report "u4u3u: " & integer'image(i) & " + " & integer'image(j) & " = "
+          & to_string(add_u4u3u);
+        report "s4s3s: " & integer'image(i) & " + " & integer'image(j) & " = "
+          & to_string(add_s4s3s);
+        report "u4s3s: " & integer'image(i) & " + " & integer'image(j) & " = "
+          & to_string(add_u4s3s);
+        report "s4u3s: " & integer'image(i) & " + " & integer'image(j) & " = "
+          & to_string(add_s4u3s);
+        report "u4iu:  " & integer'image(i) & " + " & integer'image(j) & " = "
+          & to_string(add_u4iu);
+        report "iu3u:  " & integer'image(i) & " + " & integer'image(j) & " = "
+          & to_string(add_iu3u);
+        report "s4is:  " & integer'image(i) & " + " & integer'image(j) & " = "
+          & to_string(add_s4is);
+        report "is3s:  " & integer'image(i) & " + " & integer'image(j) & " = "
+          & to_string(add_is3s);
+        report "u4lu:  " & integer'image(i) & " + " & integer'image(j mod 2) & " = "
+          & to_string(add_u4lu);
+        report "lu3u:  " & integer'image(i mod 2) & " + " & integer'image(j) & " = "
+          & to_string(add_lu3u);
+        report "s4ls:  " & integer'image(i) & " + " & integer'image(j mod 2) & " = "
+          & to_string(add_s4ls);
+        report "ls3s:  " & integer'image(i mod 2) & " + " & integer'image(j) & " = "
+          & to_string(add_ls3s);
+
+        ------
+
+        report "u4u3v: " & integer'image(i) & " + " & integer'image(j) & " = "
+          & to_string(add_u4u3v);
+        report "s4s3v: " & integer'image(i) & " + " & integer'image(j) & " = "
+          & to_string(add_s4s3v);
+        report "u4s3v: " & integer'image(i) & " + " & integer'image(j) & " = "
+          & to_string(add_u4s3v);
+        report "s4u3v: " & integer'image(i) & " + " & integer'image(j) & " = "
+          & to_string(add_s4u3v);
+        report "u4iv:  " & integer'image(i) & " + " & integer'image(j) & " = "
+          & to_string(add_u4iv);
+        report "iu3v:  " & integer'image(i) & " + " & integer'image(j) & " = "
+          & to_string(add_iu3v);
+        report "s4iv:  " & integer'image(i) & " + " & integer'image(j) & " = "
+          & to_string(add_s4iv);
+        report "is3v:  " & integer'image(i) & " + " & integer'image(j) & " = "
+          & to_string(add_is3v);
+        report "u4lv:  " & integer'image(i) & " + " & integer'image(j mod 2) & " = "
+          & to_string(add_u4lv);
+        report "lu3v:  " & integer'image(i mod 2) & " + " & integer'image(j) & " = "
+          & to_string(add_lu3v);
+        report "s4lv:  " & integer'image(i) & " + " & integer'image(j mod 2) & " = "
+          & to_string(add_s4lv);
+        report "ls3v:  " & integer'image(i mod 2) & " + " & integer'image(j) & " = "
+          & to_string(add_ls3v);
+      end loop;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/sns01/tb_cmpeq.vhdl b/testsuite/synth/sns01/tb_cmpeq.vhdl
new file mode 100644
index 000000000..f92dac5fb
--- /dev/null
+++ b/testsuite/synth/sns01/tb_cmpeq.vhdl
@@ -0,0 +1,67 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_cmpeq is
+end;
+
+architecture behav of tb_cmpeq is
+  signal li : integer := 0;
+  signal ri : integer := 0;
+  signal l4 : std_logic_vector (3 downto 0) := "0000";
+  signal r3 : std_logic_vector (2 downto 0) := "000";
+  signal eq_u4u3 : boolean;
+  signal eq_s4s3 : boolean;
+  signal eq_u4s3 : boolean;
+  signal eq_s4u3 : boolean;
+  signal eq_u4i :  boolean;
+  signal eq_iu3 :  boolean;
+  signal eq_s4i :  boolean;
+  signal eq_is3 :  boolean;
+begin
+
+  dut: entity work.cmpeq
+    port map (
+      l4 => l4,
+      r3 => r3,
+      li => li,
+      ri => ri,
+      eq_u4u3 => eq_u4u3,
+      eq_s4s3 => eq_s4s3,
+      eq_u4s3 => eq_u4s3,
+      eq_s4u3 => eq_s4u3,
+      eq_u4i => eq_u4i,
+      eq_iu3 => eq_iu3,
+      eq_s4i => eq_s4i,
+      eq_is3 => eq_is3);
+
+  process
+  begin
+    for i in -8 to 7 loop
+      li <= i;
+      l4 <= conv_std_logic_vector (i, 4);
+      for j in -4 to 3 loop
+        r3 <= conv_std_logic_vector (j, 3);
+        ri <= j;
+        wait for 1 ns;
+        report "u4u3: " & integer'image(i) & " = " & integer'image(j) & " = "
+          & boolean'image(eq_u4u3);
+        report "s4s3: " & integer'image(i) & " = " & integer'image(j) & " = "
+          & boolean'image(eq_s4s3);
+        report "u4s3: " & integer'image(i) & " = " & integer'image(j) & " = "
+          & boolean'image(eq_u4s3);
+        report "s4u3: " & integer'image(i) & " = " & integer'image(j) & " = "
+          & boolean'image(eq_s4u3);
+        report "u4i:  " & integer'image(i) & " = " & integer'image(j) & " = "
+          & boolean'image(eq_u4i);
+        report "iu3:  " & integer'image(i) & " = " & integer'image(j) & " = "
+          & boolean'image(eq_iu3);
+        report "s4i:  " & integer'image(i) & " = " & integer'image(j) & " = "
+          & boolean'image(eq_s4i);
+        report "is3:  " & integer'image(i) & " = " & integer'image(j) & " = "
+          & boolean'image(eq_is3);
+      end loop;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/sns01/tb_cmpge.vhdl b/testsuite/synth/sns01/tb_cmpge.vhdl
new file mode 100644
index 000000000..028562214
--- /dev/null
+++ b/testsuite/synth/sns01/tb_cmpge.vhdl
@@ -0,0 +1,67 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_cmpge is
+end;
+
+architecture behav of tb_cmpge is
+  signal li : integer := 0;
+  signal ri : integer := 0;
+  signal l4 : std_logic_vector (3 downto 0) := "0000";
+  signal r3 : std_logic_vector (2 downto 0) := "000";
+  signal ge_u4u3 : boolean;
+  signal ge_s4s3 : boolean;
+  signal ge_u4s3 : boolean;
+  signal ge_s4u3 : boolean;
+  signal ge_u4i :  boolean;
+  signal ge_iu3 :  boolean;
+  signal ge_s4i :  boolean;
+  signal ge_is3 :  boolean;
+begin
+
+  dut: entity work.cmpge
+    port map (
+      l4 => l4,
+      r3 => r3,
+      li => li,
+      ri => ri,
+      ge_u4u3 => ge_u4u3,
+      ge_s4s3 => ge_s4s3,
+      ge_u4s3 => ge_u4s3,
+      ge_s4u3 => ge_s4u3,
+      ge_u4i => ge_u4i,
+      ge_iu3 => ge_iu3,
+      ge_s4i => ge_s4i,
+      ge_is3 => ge_is3);
+
+  process
+  begin
+    for i in -8 to 7 loop
+      li <= i;
+      l4 <= conv_std_logic_vector (i, 4);
+      for j in -4 to 3 loop
+        r3 <= conv_std_logic_vector (j, 3);
+        ri <= j;
+        wait for 1 ns;
+        report "u4u3: " & integer'image(i) & " >= " & integer'image(j) & " = "
+          & boolean'image(ge_u4u3);
+        report "s4s3: " & integer'image(i) & " >= " & integer'image(j) & " = "
+          & boolean'image(ge_s4s3);
+        report "u4s3: " & integer'image(i) & " >= " & integer'image(j) & " = "
+          & boolean'image(ge_u4s3);
+        report "s4u3: " & integer'image(i) & " >= " & integer'image(j) & " = "
+          & boolean'image(ge_s4u3);
+        report "u4i:  " & integer'image(i) & " >= " & integer'image(j) & " = "
+          & boolean'image(ge_u4i);
+        report "iu3:  " & integer'image(i) & " >= " & integer'image(j) & " = "
+          & boolean'image(ge_iu3);
+        report "s4i:  " & integer'image(i) & " >= " & integer'image(j) & " = "
+          & boolean'image(ge_s4i);
+        report "is3:  " & integer'image(i) & " >= " & integer'image(j) & " = "
+          & boolean'image(ge_is3);
+      end loop;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/sns01/tb_cmpgt.vhdl b/testsuite/synth/sns01/tb_cmpgt.vhdl
new file mode 100644
index 000000000..a894a4cb7
--- /dev/null
+++ b/testsuite/synth/sns01/tb_cmpgt.vhdl
@@ -0,0 +1,67 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_cmpgt is
+end;
+
+architecture behav of tb_cmpgt is
+  signal li : integer := 0;
+  signal ri : integer := 0;
+  signal l4 : std_logic_vector (3 downto 0) := "0000";
+  signal r3 : std_logic_vector (2 downto 0) := "000";
+  signal gt_u4u3 : boolean;
+  signal gt_s4s3 : boolean;
+  signal gt_u4s3 : boolean;
+  signal gt_s4u3 : boolean;
+  signal gt_u4i :  boolean;
+  signal gt_iu3 :  boolean;
+  signal gt_s4i :  boolean;
+  signal gt_is3 :  boolean;
+begin
+
+  dut: entity work.cmpgt
+    port map (
+      l4 => l4,
+      r3 => r3,
+      li => li,
+      ri => ri,
+      gt_u4u3 => gt_u4u3,
+      gt_s4s3 => gt_s4s3,
+      gt_u4s3 => gt_u4s3,
+      gt_s4u3 => gt_s4u3,
+      gt_u4i => gt_u4i,
+      gt_iu3 => gt_iu3,
+      gt_s4i => gt_s4i,
+      gt_is3 => gt_is3);
+
+  process
+  begin
+    for i in -8 to 7 loop
+      li <= i;
+      l4 <= conv_std_logic_vector (i, 4);
+      for j in -4 to 3 loop
+        r3 <= conv_std_logic_vector (j, 3);
+        ri <= j;
+        wait for 1 ns;
+        report "u4u3: " & integer'image(i) & " > " & integer'image(j) & " = "
+          & boolean'image(gt_u4u3);
+        report "s4s3: " & integer'image(i) & " > " & integer'image(j) & " = "
+          & boolean'image(gt_s4s3);
+        report "u4s3: " & integer'image(i) & " > " & integer'image(j) & " = "
+          & boolean'image(gt_u4s3);
+        report "s4u3: " & integer'image(i) & " > " & integer'image(j) & " = "
+          & boolean'image(gt_s4u3);
+        report "u4i:  " & integer'image(i) & " > " & integer'image(j) & " = "
+          & boolean'image(gt_u4i);
+        report "iu3:  " & integer'image(i) & " > " & integer'image(j) & " = "
+          & boolean'image(gt_iu3);
+        report "s4i:  " & integer'image(i) & " > " & integer'image(j) & " = "
+          & boolean'image(gt_s4i);
+        report "is3:  " & integer'image(i) & " > " & integer'image(j) & " = "
+          & boolean'image(gt_is3);
+      end loop;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/sns01/tb_cmple.vhdl b/testsuite/synth/sns01/tb_cmple.vhdl
new file mode 100644
index 000000000..c60db93e0
--- /dev/null
+++ b/testsuite/synth/sns01/tb_cmple.vhdl
@@ -0,0 +1,67 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_cmple is
+end;
+
+architecture behav of tb_cmple is
+  signal li : integer := 0;
+  signal ri : integer := 0;
+  signal l4 : std_logic_vector (3 downto 0) := "0000";
+  signal r3 : std_logic_vector (2 downto 0) := "000";
+  signal le_u4u3 : boolean;
+  signal le_s4s3 : boolean;
+  signal le_u4s3 : boolean;
+  signal le_s4u3 : boolean;
+  signal le_u4i :  boolean;
+  signal le_iu3 :  boolean;
+  signal le_s4i :  boolean;
+  signal le_is3 :  boolean;
+begin
+
+  dut: entity work.cmple
+    port map (
+      l4 => l4,
+      r3 => r3,
+      li => li,
+      ri => ri,
+      le_u4u3 => le_u4u3,
+      le_s4s3 => le_s4s3,
+      le_u4s3 => le_u4s3,
+      le_s4u3 => le_s4u3,
+      le_u4i => le_u4i,
+      le_iu3 => le_iu3,
+      le_s4i => le_s4i,
+      le_is3 => le_is3);
+
+  process
+  begin
+    for i in -8 to 7 loop
+      li <= i;
+      l4 <= conv_std_logic_vector (i, 4);
+      for j in -4 to 3 loop
+        r3 <= conv_std_logic_vector (j, 3);
+        ri <= j;
+        wait for 1 ns;
+        report "u4u3: " & integer'image(i) & " <= " & integer'image(j) & " = "
+          & boolean'image(le_u4u3);
+        report "s4s3: " & integer'image(i) & " <= " & integer'image(j) & " = "
+          & boolean'image(le_s4s3);
+        report "u4s3: " & integer'image(i) & " <= " & integer'image(j) & " = "
+          & boolean'image(le_u4s3);
+        report "s4u3: " & integer'image(i) & " <= " & integer'image(j) & " = "
+          & boolean'image(le_s4u3);
+        report "u4i:  " & integer'image(i) & " <= " & integer'image(j) & " = "
+          & boolean'image(le_u4i);
+        report "iu3:  " & integer'image(i) & " <= " & integer'image(j) & " = "
+          & boolean'image(le_iu3);
+        report "s4i:  " & integer'image(i) & " <= " & integer'image(j) & " = "
+          & boolean'image(le_s4i);
+        report "is3:  " & integer'image(i) & " <= " & integer'image(j) & " = "
+          & boolean'image(le_is3);
+      end loop;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/sns01/tb_cmplt.vhdl b/testsuite/synth/sns01/tb_cmplt.vhdl
new file mode 100644
index 000000000..d8c1ee162
--- /dev/null
+++ b/testsuite/synth/sns01/tb_cmplt.vhdl
@@ -0,0 +1,67 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_cmplt is
+end;
+
+architecture behav of tb_cmplt is
+  signal li : integer := 0;
+  signal ri : integer := 0;
+  signal l4 : std_logic_vector (3 downto 0) := "0000";
+  signal r3 : std_logic_vector (2 downto 0) := "000";
+  signal lt_u4u3 : boolean;
+  signal lt_s4s3 : boolean;
+  signal lt_u4s3 : boolean;
+  signal lt_s4u3 : boolean;
+  signal lt_u4i :  boolean;
+  signal lt_iu3 :  boolean;
+  signal lt_s4i :  boolean;
+  signal lt_is3 :  boolean;
+begin
+
+  dut: entity work.cmplt
+    port map (
+      l4 => l4,
+      r3 => r3,
+      li => li,
+      ri => ri,
+      lt_u4u3 => lt_u4u3,
+      lt_s4s3 => lt_s4s3,
+      lt_u4s3 => lt_u4s3,
+      lt_s4u3 => lt_s4u3,
+      lt_u4i => lt_u4i,
+      lt_iu3 => lt_iu3,
+      lt_s4i => lt_s4i,
+      lt_is3 => lt_is3);
+
+  process
+  begin
+    for i in -8 to 7 loop
+      li <= i;
+      l4 <= conv_std_logic_vector (i, 4);
+      for j in -4 to 3 loop
+        r3 <= conv_std_logic_vector (j, 3);
+        ri <= j;
+        wait for 1 ns;
+        report "u4u3: " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(lt_u4u3);
+        report "s4s3: " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(lt_s4s3);
+        report "u4s3: " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(lt_u4s3);
+        report "s4u3: " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(lt_s4u3);
+        report "u4i:  " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(lt_u4i);
+        report "iu3:  " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(lt_iu3);
+        report "s4i:  " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(lt_s4i);
+        report "is3:  " & integer'image(i) & " < " & integer'image(j) & " = "
+          & boolean'image(lt_is3);
+      end loop;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/sns01/tb_cmpne.vhdl b/testsuite/synth/sns01/tb_cmpne.vhdl
new file mode 100644
index 000000000..8a4922f7e
--- /dev/null
+++ b/testsuite/synth/sns01/tb_cmpne.vhdl
@@ -0,0 +1,67 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_cmpne is
+end;
+
+architecture behav of tb_cmpne is
+  signal li : integer := 0;
+  signal ri : integer := 0;
+  signal l4 : std_logic_vector (3 downto 0) := "0000";
+  signal r3 : std_logic_vector (2 downto 0) := "000";
+  signal ne_u4u3 : boolean;
+  signal ne_s4s3 : boolean;
+  signal ne_u4s3 : boolean;
+  signal ne_s4u3 : boolean;
+  signal ne_u4i :  boolean;
+  signal ne_iu3 :  boolean;
+  signal ne_s4i :  boolean;
+  signal ne_is3 :  boolean;
+begin
+
+  dut: entity work.cmpne
+    port map (
+      l4 => l4,
+      r3 => r3,
+      li => li,
+      ri => ri,
+      ne_u4u3 => ne_u4u3,
+      ne_s4s3 => ne_s4s3,
+      ne_u4s3 => ne_u4s3,
+      ne_s4u3 => ne_s4u3,
+      ne_u4i => ne_u4i,
+      ne_iu3 => ne_iu3,
+      ne_s4i => ne_s4i,
+      ne_is3 => ne_is3);
+
+  process
+  begin
+    for i in -8 to 7 loop
+      li <= i;
+      l4 <= conv_std_logic_vector (i, 4);
+      for j in -4 to 3 loop
+        r3 <= conv_std_logic_vector (j, 3);
+        ri <= j;
+        wait for 1 ns;
+        report "u4u3: " & integer'image(i) & " /= " & integer'image(j) & " = "
+          & boolean'image(ne_u4u3);
+        report "s4s3: " & integer'image(i) & " /= " & integer'image(j) & " = "
+          & boolean'image(ne_s4s3);
+        report "u4s3: " & integer'image(i) & " /= " & integer'image(j) & " = "
+          & boolean'image(ne_u4s3);
+        report "s4u3: " & integer'image(i) & " /= " & integer'image(j) & " = "
+          & boolean'image(ne_s4u3);
+        report "u4i:  " & integer'image(i) & " /= " & integer'image(j) & " = "
+          & boolean'image(ne_u4i);
+        report "iu3:  " & integer'image(i) & " /= " & integer'image(j) & " = "
+          & boolean'image(ne_iu3);
+        report "s4i:  " & integer'image(i) & " /= " & integer'image(j) & " = "
+          & boolean'image(ne_s4i);
+        report "is3:  " & integer'image(i) & " /= " & integer'image(j) & " = "
+          & boolean'image(ne_is3);
+      end loop;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/sns01/tb_subs.vhdl b/testsuite/synth/sns01/tb_subs.vhdl
new file mode 100644
index 000000000..9844e8a11
--- /dev/null
+++ b/testsuite/synth/sns01/tb_subs.vhdl
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity tb_subs is
+end;
+
+architecture behav of tb_subs is
+  type sl_map_type is array (std_ulogic) of character;
+  constant sl_map : sl_map_type := "UX01ZWLH-";
+
+  function to_string(v : std_logic_vector) return string
+  is
+    alias av : std_logic_vector(1 to v'length) is v;
+    variable res : string (1 to v'length);
+  begin
+    for i in res'range loop
+      res (i) := sl_map (av (i));
+    end loop;
+    return res;
+  end to_string;
+
+  signal li : integer := 0;
+  signal ri : integer := 0;
+  signal l4 : std_logic_vector (3 downto 0) := "0000";
+  signal r3 : std_logic_vector (2 downto 0) := "000";
+  signal sub_u4u3u : std_logic_vector (3 downto 0) := "0000";
+  signal sub_s4s3s : std_logic_vector (3 downto 0) := "0000";
+  signal sub_u4s3s : std_logic_vector (4 downto 0) := "00000";
+  signal sub_s4u3s : std_logic_vector (3 downto 0) := "0000";
+  signal sub_u4iu : std_logic_vector (3 downto 0) := "0000";
+  signal sub_iu3u : std_logic_vector (2 downto 0) := "000";
+  signal sub_s4is : std_logic_vector (3 downto 0) := "0000";
+  signal sub_is3s : std_logic_vector (2 downto 0) := "000";
+  signal sub_u4lu : std_logic_vector (3 downto 0) := "0000";
+  signal sub_lu3u : std_logic_vector (2 downto 0) := "000";
+  signal sub_s4ls : std_logic_vector (3 downto 0) := "0000";
+  signal sub_ls3s : std_logic_vector (2 downto 0) := "000";
+
+  signal sub_u4u3v : std_logic_vector (3 downto 0) := "0000";
+  signal sub_s4s3v : std_logic_vector (3 downto 0) := "0000";
+  signal sub_u4s3v : std_logic_vector (4 downto 0) := "00000";
+  signal sub_s4u3v : std_logic_vector (3 downto 0) := "0000";
+  signal sub_u4iv : std_logic_vector (3 downto 0) := "0000";
+  signal sub_iu3v : std_logic_vector (2 downto 0) := "000";
+  signal sub_s4iv : std_logic_vector (3 downto 0) := "0000";
+  signal sub_is3v : std_logic_vector (2 downto 0) := "000";
+  signal sub_u4lv : std_logic_vector (3 downto 0) := "0000";
+  signal sub_lu3v : std_logic_vector (2 downto 0) := "000";
+  signal sub_s4lv : std_logic_vector (3 downto 0) := "0000";
+  signal sub_ls3v : std_logic_vector (2 downto 0) := "000";
+begin
+
+  dut: entity work.subs
+    port map (
+      l4 => l4,
+      r3 => r3,
+      li => li,
+      ri => ri,
+      sub_u4u3u => sub_u4u3u,
+      sub_s4s3s => sub_s4s3s,
+      sub_u4s3s => sub_u4s3s,
+      sub_s4u3s => sub_s4u3s,
+      sub_u4iu => sub_u4iu,
+      sub_iu3u => sub_iu3u,
+      sub_s4is => sub_s4is,
+      sub_is3s => sub_is3s,
+      sub_u4lu => sub_u4lu,
+      sub_lu3u => sub_lu3u,
+      sub_s4ls => sub_s4ls,
+      sub_ls3s => sub_ls3s,
+
+      sub_u4u3v => sub_u4u3v,
+      sub_s4s3v => sub_s4s3v,
+      sub_u4s3v => sub_u4s3v,
+      sub_s4u3v => sub_s4u3v,
+      sub_u4iv => sub_u4iv,
+      sub_iu3v => sub_iu3v,
+      sub_s4iv => sub_s4iv,
+      sub_is3v => sub_is3v,
+      sub_u4lv => sub_u4lv,
+      sub_lu3v => sub_lu3v,
+      sub_s4lv => sub_s4lv,
+      sub_ls3v => sub_ls3v);
+
+  process
+  begin
+    for i in -8 to 7 loop
+      li <= i;
+      l4 <= conv_std_logic_vector (i, 4);
+      for j in -4 to 3 loop
+        r3 <= conv_std_logic_vector (j, 3);
+        ri <= j;
+        wait for 1 ns;
+        report "u4u3u: " & integer'image(i) & " - " & integer'image(j) & " = "
+          & to_string(sub_u4u3u);
+        report "s4s3s: " & integer'image(i) & " - " & integer'image(j) & " = "
+          & to_string(sub_s4s3s);
+        report "u4s3s: " & integer'image(i) & " - " & integer'image(j) & " = "
+          & to_string(sub_u4s3s);
+        report "s4u3s: " & integer'image(i) & " - " & integer'image(j) & " = "
+          & to_string(sub_s4u3s);
+        report "u4iu:  " & integer'image(i) & " - " & integer'image(j) & " = "
+          & to_string(sub_u4iu);
+        report "iu3u:  " & integer'image(i) & " - " & integer'image(j) & " = "
+          & to_string(sub_iu3u);
+        report "s4is:  " & integer'image(i) & " - " & integer'image(j) & " = "
+          & to_string(sub_s4is);
+        report "is3s:  " & integer'image(i) & " - " & integer'image(j) & " = "
+          & to_string(sub_is3s);
+        report "u4lu:  " & integer'image(i) & " - " & integer'image(j mod 2) & " = "
+          & to_string(sub_u4lu);
+        report "lu3u:  " & integer'image(i mod 2) & " - " & integer'image(j) & " = "
+          & to_string(sub_lu3u);
+        report "s4ls:  " & integer'image(i) & " - " & integer'image(j mod 2) & " = "
+          & to_string(sub_s4ls);
+        report "ls3s:  " & integer'image(i mod 2) & " - " & integer'image(j) & " = "
+          & to_string(sub_ls3s);
+
+        ------
+
+        report "u4u3v: " & integer'image(i) & " - " & integer'image(j) & " = "
+          & to_string(sub_u4u3v);
+        report "s4s3v: " & integer'image(i) & " - " & integer'image(j) & " = "
+          & to_string(sub_s4s3v);
+        report "u4s3v: " & integer'image(i) & " - " & integer'image(j) & " = "
+          & to_string(sub_u4s3v);
+        report "s4u3v: " & integer'image(i) & " - " & integer'image(j) & " = "
+          & to_string(sub_s4u3v);
+        report "u4iv:  " & integer'image(i) & " - " & integer'image(j) & " = "
+          & to_string(sub_u4iv);
+        report "iu3v:  " & integer'image(i) & " - " & integer'image(j) & " = "
+          & to_string(sub_iu3v);
+        report "s4iv:  " & integer'image(i) & " - " & integer'image(j) & " = "
+          & to_string(sub_s4iv);
+        report "is3v:  " & integer'image(i) & " - " & integer'image(j) & " = "
+          & to_string(sub_is3v);
+        report "u4lv:  " & integer'image(i) & " - " & integer'image(j mod 2) & " = "
+          & to_string(sub_u4lv);
+        report "lu3v:  " & integer'image(i mod 2) & " - " & integer'image(j) & " = "
+          & to_string(sub_lu3v);
+        report "s4lv:  " & integer'image(i) & " - " & integer'image(j mod 2) & " = "
+          & to_string(sub_s4lv);
+        report "ls3v:  " & integer'image(i mod 2) & " - " & integer'image(j) & " = "
+          & to_string(sub_ls3v);
+      end loop;
+    end loop;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/sns01/testsuite.sh b/testsuite/synth/sns01/testsuite.sh
index a93cc4530..c6f573dd1 100755
--- a/testsuite/synth/sns01/testsuite.sh
+++ b/testsuite/synth/sns01/testsuite.sh
@@ -4,6 +4,19 @@
 
 GHDL_STD_FLAGS=-fsynopsys
 
+# Compare opers.
+for f in adds subs cmplt cmple cmpgt cmpge cmpeq cmpne; do
+    analyze $f.vhdl
+    analyze tb_$f.vhdl
+    elab_simulate tb_$f > $f.ref
+
+    synth $f.vhdl -e > syn_$f.vhdl
+    analyze tb_$f.vhdl
+    elab_simulate tb_$f > $f.out
+
+    diff --strip-trailing-cr $f.out $f.ref
+done
+
 for t in sns01; do
     synth $t.vhdl -e $t > syn_$t.vhdl
     # No analysis because of conflict between numeric_std.unsigned and