testsuite/synth: add a test for #1426

2 files changed, 63 insertions, 0 deletions

diff --git a/testsuite/synth/issue1426/bar.vhdl b/testsuite/synth/issue1426/bar.vhdl
new file mode 100644
index 000000000..a75a10f9b
--- /dev/null
+++ b/testsuite/synth/issue1426/bar.vhdl
@@ -0,0 +1,55 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;	 
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;   
+
+entity bar is
+	generic(
+		Clk_freq 	: integer := 50;
+		Bit_rate 	: integer := 460800
+		);
+    port (
+		rst_i 		: in std_logic;
+		clk_i 		: in std_logic;	 
+		start_i     : in std_logic;
+    	output      : out std_logic_vector(5 downto 0)
+  	);
+end bar;
+
+architecture bar of bar is
+
+constant Freq_ratio 	: integer := Clk_freq*(10**6)/Bit_rate;
+signal period_counter	: std_logic_vector(5 downto 0);
+signal res			    : std_logic_vector(5 downto 0);
+
+begin
+counter: process(rst_i, clk_i)
+begin		
+	if rst_i = '1' then
+		period_counter <= (others => '0');
+	elsif rising_edge(clk_i) then
+		if start_i = '1' then 
+			if period_counter /= freq_ratio - 1 then
+				period_counter <= period_counter + 1;
+			else
+				period_counter <= (others => '0');
+			end if;	
+		else
+			period_counter <= (others => '0');
+		end if;	  
+	end if;
+end process;	
+result: process(rst_i, clk_i)
+begin		
+	if rst_i = '1' then
+		res <= conv_std_logic_vector(0, 6);
+	elsif rising_edge(clk_i) then  
+		if start_i = '1' then
+			res <= period_counter; 							
+		else	
+			res <= conv_std_logic_vector(0, 6);				
+		end if;	
+	end if;
+end process;	
+output <= res;
+end bar;
diff --git a/testsuite/synth/issue1426/testsuite.sh b/testsuite/synth/issue1426/testsuite.sh
new file mode 100755
index 000000000..ad39f7eff
--- /dev/null
+++ b/testsuite/synth/issue1426/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=-fsynopsys
+synth bar.vhdl -e > syn_bar.vhdl
+
+echo "Test successful"