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author | Tristan Gingold <tgingold@free.fr> | 2016-03-19 07:19:06 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2016-03-19 07:19:06 +0100 |
commit | cad9787131816bd1fb7f7532caef28402d79a681 (patch) | |
tree | c6615a6703cac60551753f67827e657e1d8e89af /testsuite | |
parent | 368b69c1a09413795a1409d6b54d02139d9fa519 (diff) | |
download | ghdl-cad9787131816bd1fb7f7532caef28402d79a681.tar.gz ghdl-cad9787131816bd1fb7f7532caef28402d79a681.tar.bz2 ghdl-cad9787131816bd1fb7f7532caef28402d79a681.zip |
Add testcase for issue45.
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/gna/issue45/test1.vhdl | 57 | ||||
-rwxr-xr-x | testsuite/gna/issue45/testsuite.sh | 15 |
2 files changed, 72 insertions, 0 deletions
diff --git a/testsuite/gna/issue45/test1.vhdl b/testsuite/gna/issue45/test1.vhdl new file mode 100644 index 000000000..1b011d7c2 --- /dev/null +++ b/testsuite/gna/issue45/test1.vhdl @@ -0,0 +1,57 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library std; +use std.env.all; + + +entity psl_test_endpoint is +end entity psl_test_endpoint; + + +architecture test of psl_test_endpoint is + + + signal s_rst_n : std_logic := '0'; + signal s_clk : std_logic := '0'; + signal s_write : std_logic; + signal s_read : std_logic; + + +begin + + + s_rst_n <= '1' after 100 ns; + s_clk <= not s_clk after 10 ns; + + + TestP : process is + begin + report "RUNNING psl_test_endpoint test case"; + report "=========================================="; + s_write <= '0'; -- named assertion should hit + s_read <= '0'; + wait until s_rst_n = '1' and rising_edge(s_clk); + s_write <= '1'; + wait until rising_edge(s_clk); + s_read <= '1'; -- assertion should hit + wait until rising_edge(s_clk); + s_write <= '0'; + s_read <= '0'; + wait until rising_edge(s_clk); + stop(0); + end process TestP; + + + -- psl default clock is rising_edge(s_clk); + -- psl endpoint E_TEST is {not(s_write); s_write}; + -- psl sequence abc_seq is {not(s_write); s_write}; + + -- psl ENDPOINT_ASSERT : assert always {E_TEST; s_read} report "ENDPOINT ASSERT"; + -- psl COVERAGE0 : cover {not(s_write); s_write} report "COVERED0"; + -- psl COVERAGE1 : cover {abc_seq} report "COVERED1"; + -- psl COVERAGE2 : cover {E_TEST} report "COVERED2"; + + +end architecture test; diff --git a/testsuite/gna/issue45/testsuite.sh b/testsuite/gna/issue45/testsuite.sh new file mode 100755 index 000000000..71bfe447b --- /dev/null +++ b/testsuite/gna/issue45/testsuite.sh @@ -0,0 +1,15 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS="--std=08 -fpsl" + +analyze test1.vhdl +elab_simulate psl_test_endpoint --psl-report=psl.out + +grep -q '"cover-pass": 3' psl.out +rm psl.out + +clean + +echo "Test successful" |