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author | Tristan Gingold <tgingold@free.fr> | 2020-03-10 19:26:20 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-10 19:26:20 +0100 |
commit | c7fc6185ae789e248c0752577ca44e6100616399 (patch) | |
tree | 9caa4eed4951ff38a523822073571d6c89ac4c91 /testsuite | |
parent | 3ea034dfb17430430b49000f4d9e4d54032e4b3e (diff) | |
download | ghdl-c7fc6185ae789e248c0752577ca44e6100616399.tar.gz ghdl-c7fc6185ae789e248c0752577ca44e6100616399.tar.bz2 ghdl-c7fc6185ae789e248c0752577ca44e6100616399.zip |
testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite')
-rwxr-xr-x | testsuite/synth/slice01/testsuite.sh | 9 | ||||
-rw-r--r-- | testsuite/synth/slice02/slice01.vhdl | 16 | ||||
-rw-r--r-- | testsuite/synth/slice02/slice02.vhdl | 16 | ||||
-rw-r--r-- | testsuite/synth/slice02/tb_slice01.vhdl | 22 | ||||
-rw-r--r-- | testsuite/synth/slice02/tb_slice02.vhdl | 22 | ||||
-rwxr-xr-x | testsuite/synth/slice02/testsuite.sh | 9 |
6 files changed, 86 insertions, 8 deletions
diff --git a/testsuite/synth/slice01/testsuite.sh b/testsuite/synth/slice01/testsuite.sh index dcaf3f202..828ebcc62 100755 --- a/testsuite/synth/slice01/testsuite.sh +++ b/testsuite/synth/slice01/testsuite.sh @@ -3,14 +3,7 @@ . ../../testenv.sh for t in slice01 slice02 slice03; do - analyze $t.vhdl tb_$t.vhdl - elab_simulate tb_$t - clean - - synth $t.vhdl -e $t > syn_$t.vhdl - analyze syn_$t.vhdl tb_$t.vhdl - elab_simulate tb_$t --ieee-asserts=disable-at-0 - clean + synth_tb $t done echo "Test successful" diff --git a/testsuite/synth/slice02/slice01.vhdl b/testsuite/synth/slice02/slice01.vhdl new file mode 100644 index 000000000..e2338cd69 --- /dev/null +++ b/testsuite/synth/slice02/slice01.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity slice01 is + port (di : std_logic_vector(7 downto 0); + do : out std_logic_vector (3 downto 0)); +end slice01; + +architecture behav of slice01 is + type mem is array (natural range <>) of std_logic_vector (1 downto 0); + signal m1, m2 : mem (3 downto 0); +begin + m1 <= (di (7 downto 6), di (5 downto 4), di (3 downto 2), di (1 downto 0)); + m2 <= (m1 (0), m1 (1), m1 (2), m1 (3)); + do <= m2 (1) & m2 (0); +end behav; diff --git a/testsuite/synth/slice02/slice02.vhdl b/testsuite/synth/slice02/slice02.vhdl new file mode 100644 index 000000000..6c78f67bf --- /dev/null +++ b/testsuite/synth/slice02/slice02.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity slice02 is + port (di : std_logic_vector(7 downto 0); + do : out std_logic_vector (3 downto 0)); +end slice02; + +architecture behav of slice02 is + type mem is array (natural range <>) of std_logic_vector (1 downto 0); + signal m1, m2 : mem (3 downto 0); +begin + m1 <= (di (7 downto 6), di (5 downto 4), di (3 downto 2), di (1 downto 0)); + m2 <= m1 (0 downto 0) & m1 (1 downto 1) & m1 (2 downto 2) & m1 (3 downto 3); + do <= m2 (1) & m2 (0); +end behav; diff --git a/testsuite/synth/slice02/tb_slice01.vhdl b/testsuite/synth/slice02/tb_slice01.vhdl new file mode 100644 index 000000000..ec684fba0 --- /dev/null +++ b/testsuite/synth/slice02/tb_slice01.vhdl @@ -0,0 +1,22 @@ +entity tb_slice01 is +end tb_slice01; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_slice01 is + signal di : std_logic_vector (7 downto 0); + signal do : std_logic_vector (3 downto 0); +begin + dut: entity work.slice01 + port map (di, do); + + process + begin + di <= b"11_10_01_00"; + wait for 1 ns; + assert do = b"10_11" severity error; + + wait; + end process; +end behav; diff --git a/testsuite/synth/slice02/tb_slice02.vhdl b/testsuite/synth/slice02/tb_slice02.vhdl new file mode 100644 index 000000000..38cb294a3 --- /dev/null +++ b/testsuite/synth/slice02/tb_slice02.vhdl @@ -0,0 +1,22 @@ +entity tb_slice02 is +end tb_slice02; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_slice02 is + signal di : std_logic_vector (7 downto 0); + signal do : std_logic_vector (3 downto 0); +begin + dut: entity work.slice02 + port map (di, do); + + process + begin + di <= b"11_10_01_00"; + wait for 1 ns; + assert do = b"10_11" severity error; + + wait; + end process; +end behav; diff --git a/testsuite/synth/slice02/testsuite.sh b/testsuite/synth/slice02/testsuite.sh new file mode 100755 index 000000000..c29abee8b --- /dev/null +++ b/testsuite/synth/slice02/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in slice01 slice02; do + synth_tb $t +done + +echo "Test successful" |