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author | Tristan Gingold <tgingold@free.fr> | 2022-04-05 19:15:57 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-04-05 19:15:57 +0200 |
commit | c6163507c69c9b33188876224a1f615d43a94712 (patch) | |
tree | 9b6c60c275cc1a5aa211e89d49a39ac4a6a90699 /testsuite | |
parent | 9b14c0ac67981ca6db6c6d4861035afca1595965 (diff) | |
download | ghdl-c6163507c69c9b33188876224a1f615d43a94712.tar.gz ghdl-c6163507c69c9b33188876224a1f615d43a94712.tar.bz2 ghdl-c6163507c69c9b33188876224a1f615d43a94712.zip |
testsuite/synth: add tests for #2021
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/synth/issue2021/ent.vhdl | 19 | ||||
-rw-r--r-- | testsuite/synth/issue2021/repro1.vhdl | 15 | ||||
-rw-r--r-- | testsuite/synth/issue2021/repro2.vhdl | 17 | ||||
-rwxr-xr-x | testsuite/synth/issue2021/testsuite.sh | 10 |
4 files changed, 61 insertions, 0 deletions
diff --git a/testsuite/synth/issue2021/ent.vhdl b/testsuite/synth/issue2021/ent.vhdl new file mode 100644 index 000000000..71c105feb --- /dev/null +++ b/testsuite/synth/issue2021/ent.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ent is +end ent; + +architecture ent of ent is + type my_record is record + field_a : std_logic_vector; -- Parametrized on instantiation + field_b : std_logic_vector(31 downto 0); -- Width set by generic + end record; + + signal bar : my_record(field_a(7 downto 0)); + signal baz : my_record(field_a(7 downto 0)); + +begin + +end ent; diff --git a/testsuite/synth/issue2021/repro1.vhdl b/testsuite/synth/issue2021/repro1.vhdl new file mode 100644 index 000000000..0344f41cd --- /dev/null +++ b/testsuite/synth/issue2021/repro1.vhdl @@ -0,0 +1,15 @@ +entity ent is +end ent; + +architecture ent of ent is + type my_record is record + field_a : bit_vector; -- Parametrized on instantiation + field_b : bit_vector(31 downto 0); -- Width set by generic + end record; + + signal bar : my_record(field_a(7 downto 0)); + signal baz : my_record(field_a(7 downto 0)); + +begin + +end ent; diff --git a/testsuite/synth/issue2021/repro2.vhdl b/testsuite/synth/issue2021/repro2.vhdl new file mode 100644 index 000000000..5f59f8dcf --- /dev/null +++ b/testsuite/synth/issue2021/repro2.vhdl @@ -0,0 +1,17 @@ +entity repro2 is +end; + +architecture ent of repro2 is + type my_record is record + field_a : bit_vector; -- Parametrized on instantiation + field_b : bit_vector; + end record; + + subtype my_record1 is my_record (field_b(3 downto 0)); + + signal bar : my_record1(field_a(7 downto 0)); + signal baz : my_record1(field_a(7 downto 0)); + +begin + +end ent; diff --git a/testsuite/synth/issue2021/testsuite.sh b/testsuite/synth/issue2021/testsuite.sh new file mode 100755 index 000000000..c6c6c1ddf --- /dev/null +++ b/testsuite/synth/issue2021/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth_only repro1 +synth_only repro2 +synth_only ent + +echo "Test successful" |