testsuite/gna: add tests for #2244

5 files changed, 180 insertions, 0 deletions

diff --git a/testsuite/gna/issue2244/mve.vhdl b/testsuite/gna/issue2244/mve.vhdl
new file mode 100644
index 000000000..ef66cc197
--- /dev/null
+++ b/testsuite/gna/issue2244/mve.vhdl
@@ -0,0 +1,54 @@
+library ieee;
+use ieee.numeric_std.all;
+use ieee.std_logic_1164.all;
+
+
+entity mve is
+
+end mve;
+
+architecture rtl of mve is
+    signal c_a : std_logic_vector(11 downto 0) := x"FAE";
+    signal c_b : std_logic_vector(11 downto 0) := x"182";
+
+    signal s_expected_vector : std_logic_vector(31 downto 0);
+    signal s_resulting_vector : std_logic_vector(31 downto 0);
+begin
+    -- Compute expected value using intermediate variables for padding
+    expected_value : process
+        variable v_a_padded : std_logic_vector(15 downto 0);
+        variable v_b_padded : std_logic_vector(15 downto 0);
+    begin
+        v_a_padded := (15 downto 12 => c_a(11), 11 downto 0 => c_a);
+        v_b_padded := (15 downto 12 => c_b(11), 11 downto 0 => c_b);
+
+        s_expected_vector <= v_a_padded & v_b_padded;
+
+        wait for 1 ns;
+
+        report "Expected result " & to_hstring(s_expected_vector) severity note;
+
+        wait;
+    end process;
+
+    -- Perform the concatenation and the padding in 1 line
+    resulting_value : process
+    begin
+        s_resulting_vector <=
+            (15 downto 12 => c_a(11), 11 downto 0 => c_a) &
+            (15 downto 12 => c_b(11), 11 downto 0 => c_b);
+
+        wait for 2 ns;
+
+        report "Actual result " & to_hstring(s_resulting_vector) severity note;
+
+        wait;
+    end process;
+
+    checker : process
+    begin
+        wait for 3 ns;
+        assert s_resulting_vector = s_expected_vector severity failure;
+        wait;
+    end process;
+end rtl;
diff --git a/testsuite/gna/issue2244/repro1.vhdl b/testsuite/gna/issue2244/repro1.vhdl
new file mode 100644
index 000000000..212068679
--- /dev/null
+++ b/testsuite/gna/issue2244/repro1.vhdl
@@ -0,0 +1,53 @@
+library ieee;
+use ieee.numeric_std.all;
+use ieee.std_logic_1164.all;
+
+
+entity repro1 is
+
+end repro1;
+
+architecture rtl of repro1 is
+    constant c_a : std_logic_vector(11 downto 0) := x"FAE";
+    constant c_b : std_logic_vector(11 downto 0) := x"182";
+
+    signal s_expected_vector : std_logic_vector(31 downto 0);
+    signal s_resulting_vector : std_logic_vector(31 downto 0);
+begin
+    -- Compute expected value using intermediate variables for padding
+    expected_value : process
+        variable v_a_padded : std_logic_vector(15 downto 0);
+        variable v_b_padded : std_logic_vector(15 downto 0);
+    begin
+        v_a_padded := (15 downto 12 => c_a(11), 11 downto 0 => c_a);
+        v_b_padded := (15 downto 12 => c_b(11), 11 downto 0 => c_b);
+
+        s_expected_vector <= v_a_padded & v_b_padded;
+
+        wait for 1 ns;
+
+        report "Expected result " & to_hstring(s_expected_vector) severity note;
+
+        wait;
+    end process;
+
+    -- Perform the concatenation and the padding in 1 line
+    resulting_value : process
+    begin
+        s_resulting_vector <=
+            (15 downto 12 => c_a(11), 11 downto 0 => c_a) &
+            (15 downto 12 => c_b(11), 11 downto 0 => c_b);
+
+        wait for 2 ns;
+
+        report "Actual result " & to_hstring(s_resulting_vector) severity note;
+
+        wait;
+    end process;
+
+    checker : process
+    begin
+        wait for 3 ns;
+        assert s_resulting_vector = s_expected_vector severity failure;
+    end process;
+end rtl;
diff --git a/testsuite/gna/issue2244/repro2.vhdl b/testsuite/gna/issue2244/repro2.vhdl
new file mode 100644
index 000000000..6aed8bdca
--- /dev/null
+++ b/testsuite/gna/issue2244/repro2.vhdl
@@ -0,0 +1,37 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro2 is
+end repro2;
+
+architecture rtl of repro2 is
+    signal c_a : std_logic_vector(11 downto 0) := x"FAE";
+    signal c_b : std_logic_vector(11 downto 0) := x"182";
+begin
+    expected_value : process
+        variable v_a_padded : std_logic_vector(15 downto 0);
+        variable v_b_padded : std_logic_vector(15 downto 0);
+        variable s_expected_vector : std_logic_vector(31 downto 0);
+        variable s_resulting_vector : std_logic_vector(31 downto 0);
+    begin
+        v_a_padded := (15 downto 12 => c_a(11), 11 downto 0 => c_a);
+        v_b_padded := (15 downto 12 => c_b(11), 11 downto 0 => c_b);
+
+        s_expected_vector := v_a_padded & v_b_padded;
+        report "Expected result " & to_hstring(s_expected_vector) severity note;
+
+        s_resulting_vector :=
+          (15 downto 12 => c_a(11), 11 downto 0 => c_a) &
+          (15 downto 12 => c_b(11), 11 downto 0 => c_b);
+        report "Actual result " & to_hstring(s_resulting_vector) severity note;
+
+        assert s_resulting_vector = s_expected_vector severity error;
+
+        s_resulting_vector :=
+          v_a_padded & (15 downto 12 => c_b(11), 11 downto 0 => c_b);
+        report "Actual result " & to_hstring(s_resulting_vector) severity note;
+
+        assert s_resulting_vector = s_expected_vector severity error; --failure;
+        wait;
+    end process;
+end rtl;
diff --git a/testsuite/gna/issue2244/repro3.vhdl b/testsuite/gna/issue2244/repro3.vhdl
new file mode 100644
index 000000000..a3a4879a3
--- /dev/null
+++ b/testsuite/gna/issue2244/repro3.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro3 is
+end repro3;
+
+architecture rtl of repro3 is
+    signal c_a : std_logic_vector(11 downto 0) := x"FAE";
+
+    procedure check (v : std_logic_vector) is
+    begin
+      report "v = " & to_hstring (v);
+      assert v'ascending = false report "bad direction" severity failure;
+    end check;
+begin
+    expected_value : process
+    begin
+      check ((15 downto 12 => c_a(11), 11 downto 0 => c_a));
+        wait;
+    end process;
+end rtl;
diff --git a/testsuite/gna/issue2244/testsuite.sh b/testsuite/gna/issue2244/testsuite.sh
new file mode 100755
index 000000000..22b2b5bae
--- /dev/null
+++ b/testsuite/gna/issue2244/testsuite.sh
@@ -0,0 +1,15 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+
+# TODO: repro1
+for f in mve  repro2 repro3; do
+    analyze $f.vhdl
+    elab_simulate $f
+done
+
+clean
+
+echo "Test successful"