testsuite/synth: add test for #1155

4 files changed, 132 insertions, 0 deletions

diff --git a/testsuite/synth/issue1155/ent.vhdl b/testsuite/synth/issue1155/ent.vhdl
new file mode 100644
index 000000000..40eff6347
--- /dev/null
+++ b/testsuite/synth/issue1155/ent.vhdl
@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ent is
+	port (
+		clk   : in std_logic;
+		write : in std_logic;
+
+		addr       : in std_logic_vector(1 downto 0);
+		data_write : in std_logic_vector(3 downto 0);
+
+		x0 : out std_logic_vector(3 downto 0);
+		x1 : out std_logic_vector(3 downto 0);
+		x2 : out std_logic_vector(3 downto 0);
+		x3 : out std_logic_vector(3 downto 0)
+	);
+end;
+
+architecture a of ent is
+	type store_t is array(0 to 3) of std_logic_vector(3 downto 0);
+	signal store : store_t;
+begin
+	process(clk)
+	begin
+		if rising_edge(clk) and write = '1' then
+			store(to_integer(unsigned(addr))) <= data_write;
+		end if;
+	end process;
+
+	x0 <= store(0);
+	x1 <= store(1);
+	x2 <= store(2);
+	x3 <= store(3);
+end;
diff --git a/testsuite/synth/issue1155/tb_ent.vhdl b/testsuite/synth/issue1155/tb_ent.vhdl
new file mode 100644
index 000000000..f91162ad7
--- /dev/null
+++ b/testsuite/synth/issue1155/tb_ent.vhdl
@@ -0,0 +1,74 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb_ent is
+end;
+
+architecture a of tb_ent is
+	component ent is
+		port (
+			clk   : in std_logic;
+			write : in std_logic;
+
+			addr       : in std_logic_vector(1 downto 0);
+			data_write : in std_logic_vector(3 downto 0);
+
+			x0 : out std_logic_vector(3 downto 0);
+			x1 : out std_logic_vector(3 downto 0);
+			x2 : out std_logic_vector(3 downto 0);
+			x3 : out std_logic_vector(3 downto 0)
+		);
+	end component;
+
+	signal clk, write : std_logic;
+	signal addr       : std_logic_vector(1 downto 0);
+	signal data_write : std_logic_vector(3 downto 0);
+	signal x0, x1, x2, x3 : std_logic_vector(3 downto 0);
+begin
+	uut_inst: ent
+		port map (
+			clk   => clk,
+			write => write,
+
+			addr => addr,
+			data_write => data_write,
+
+			x0 => x0,
+			x1 => x1,
+			x2 => x2,
+			x3 => x3
+		);
+
+	process
+		procedure pulse is
+		begin
+			clk <= '0';
+			wait for 10 ns;
+			clk <= '1';
+			wait for 10 ns;
+		end;
+	begin
+		write <= '0';
+		addr <= "00";
+
+		pulse;
+
+		write <= '1';
+		data_write <= "1111";
+
+		pulse;
+
+		assert x0 = "1111";
+
+		write <= '0';
+		data_write <= "0001";
+
+		pulse;
+
+		assert x0 = "1111";
+
+		wait for 20 ns;
+
+		wait;
+	end process;
+end;
diff --git a/testsuite/synth/issue1155/testsuite.sh b/testsuite/synth/issue1155/testsuite.sh
new file mode 100755
index 000000000..5c1da263d
--- /dev/null
+++ b/testsuite/synth/issue1155/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_tb ent
+
+echo "Test successful"
diff --git a/testsuite/testenv.sh b/testsuite/testenv.sh
index 93009984b..d95644dc3 100644
--- a/testsuite/testenv.sh
+++ b/testsuite/testenv.sh
@@ -116,6 +116,22 @@ synth_analyze()
     analyze syn_$1.vhdl
 }
 
+# Analyze and test $1
+# Then synthesize and test the result
+synth_tb()
+{
+    t=$1
+
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+}
+
 # Check if a feature is present
 ghdl_has_feature ()
 {