testsuite/synth: add a test for ghdl/ghdl-yosys-plugin#129

3 files changed, 55 insertions, 0 deletions

diff --git a/testsuite/synth/synth129/tb_test.vhdl b/testsuite/synth/synth129/tb_test.vhdl
new file mode 100644
index 000000000..80b6146fc
--- /dev/null
+++ b/testsuite/synth/synth129/tb_test.vhdl
@@ -0,0 +1,27 @@
+entity tb_test is
+end tb_test;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture behav of tb_test is
+  signal s : std_logic := '0';
+  signal a : unsigned(7 downto 0);
+  signal r : integer range 0 to 255;
+begin
+  dut: entity work.test
+    port map (s, a, r);
+
+  process
+  begin
+    wait for 1 ns;
+    assert r = 0 severity failure;
+
+    s <= '1';
+    a <= x"a5";
+    wait for 1 ns;
+    assert r = 165 severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/synth129/test.vhdl b/testsuite/synth/synth129/test.vhdl
new file mode 100644
index 000000000..841d11858
--- /dev/null
+++ b/testsuite/synth/synth129/test.vhdl
@@ -0,0 +1,19 @@
+library ieee;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+
+entity test is
+	port(
+		sel: 			in std_logic;
+		inp:			in unsigned(7 downto 0);
+		outp:			out integer range 0 to 255
+		);
+end;
+
+architecture a of test is
+
+begin
+	with sel select outp <= to_integer(inp) when '1', 0 when others;		
+end;	
+
diff --git a/testsuite/synth/synth129/testsuite.sh b/testsuite/synth/synth129/testsuite.sh
new file mode 100755
index 000000000..6fc5761f5
--- /dev/null
+++ b/testsuite/synth/synth129/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in test; do
+    synth_tb $t
+done
+
+echo "Test successful"