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author | Tristan Gingold <tgingold@free.fr> | 2019-07-24 07:30:33 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-07-24 07:30:33 +0200 |
commit | a679e4d670f2dfea33753e03fdbff1d223f3034b (patch) | |
tree | cdce00286748b4823e2c32d4293b8e2ccd747586 /testsuite | |
parent | ad603ca5e806e14f200a508da9d79620b45e22f0 (diff) | |
download | ghdl-a679e4d670f2dfea33753e03fdbff1d223f3034b.tar.gz ghdl-a679e4d670f2dfea33753e03fdbff1d223f3034b.tar.bz2 ghdl-a679e4d670f2dfea33753e03fdbff1d223f3034b.zip |
synth: add testcase for pragma translate_off.
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/synth/pragma01/pragma01.vhdl | 15 | ||||
-rw-r--r-- | testsuite/synth/pragma01/tb_pragma01_sim.vhdl | 19 | ||||
-rw-r--r-- | testsuite/synth/pragma01/tb_pragma01_syn.vhdl | 19 | ||||
-rwxr-xr-x | testsuite/synth/pragma01/testsuite.sh | 16 |
4 files changed, 69 insertions, 0 deletions
diff --git a/testsuite/synth/pragma01/pragma01.vhdl b/testsuite/synth/pragma01/pragma01.vhdl new file mode 100644 index 000000000..7994e8095 --- /dev/null +++ b/testsuite/synth/pragma01/pragma01.vhdl @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity pragma01 is + port (is_sim : out std_logic); +end pragma01; + +architecture behav of pragma01 is +begin + is_sim <= '0' + -- pragma translate_off + or '1' + -- pragma translate_on + ; +end behav; diff --git a/testsuite/synth/pragma01/tb_pragma01_sim.vhdl b/testsuite/synth/pragma01/tb_pragma01_sim.vhdl new file mode 100644 index 000000000..b85cc351f --- /dev/null +++ b/testsuite/synth/pragma01/tb_pragma01_sim.vhdl @@ -0,0 +1,19 @@ +entity tb_pragma01_sim is +end tb_pragma01_sim; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_pragma01_sim is + signal is_sim : std_logic; +begin + dut: entity work.pragma01 + port map (is_sim); + + process + begin + wait for 1 ns; + assert is_sim = '1' severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/pragma01/tb_pragma01_syn.vhdl b/testsuite/synth/pragma01/tb_pragma01_syn.vhdl new file mode 100644 index 000000000..4540bd5a7 --- /dev/null +++ b/testsuite/synth/pragma01/tb_pragma01_syn.vhdl @@ -0,0 +1,19 @@ +entity tb_pragma01_syn is +end tb_pragma01_syn; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_pragma01_syn is + signal is_sim : std_logic; +begin + dut: entity work.pragma01 + port map (is_sim); + + process + begin + wait for 1 ns; + assert is_sim = '0' severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/pragma01/testsuite.sh b/testsuite/synth/pragma01/testsuite.sh new file mode 100755 index 000000000..2123f3e39 --- /dev/null +++ b/testsuite/synth/pragma01/testsuite.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +. ../../testenv.sh + +for t in pragma01; do + analyze $t.vhdl tb_${t}_sim.vhdl + elab_simulate tb_${t}_sim + clean + + synth $t.vhdl -e $t > syn_$t.vhdl + analyze syn_$t.vhdl tb_${t}_syn.vhdl + elab_simulate tb_${t}_syn + clean +done + +echo "Test successful" |