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authorTristan Gingold <tgingold@free.fr>2021-06-17 08:15:44 +0200
committerTristan Gingold <tgingold@free.fr>2021-06-17 08:15:44 +0200
commit9772172e61165bb0aec9cd9cf63d1b491a584eba (patch)
treedf6d682cec508225ae318cd3babb3c2eb60ac686 /testsuite
parent067952e4214e82060f9b98032870ae8c13eee79a (diff)
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testsuite/synth: add another test on if statements
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/synth/if03/if01.vhdl27
-rw-r--r--testsuite/synth/if03/tb_if01.vhdl58
-rwxr-xr-xtestsuite/synth/if03/testsuite.sh7
3 files changed, 92 insertions, 0 deletions
diff --git a/testsuite/synth/if03/if01.vhdl b/testsuite/synth/if03/if01.vhdl
new file mode 100644
index 000000000..b1d692d7f
--- /dev/null
+++ b/testsuite/synth/if03/if01.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity if01 is
+ port (a : std_logic;
+ b : std_logic;
+ en1 : std_logic;
+ sel1 : std_logic;
+ clk : std_logic;
+ s1 : out std_logic;
+ s2 : out std_logic);
+end if01;
+
+architecture behav of if01 is
+begin
+ process (clk) is
+ variable t : std_logic;
+ begin
+ if rising_edge(clk) then
+ if en1 = '1' then
+ t := b;
+ s1 <= a;
+ end if;
+ s2 <= t;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/synth/if03/tb_if01.vhdl b/testsuite/synth/if03/tb_if01.vhdl
new file mode 100644
index 000000000..c81f109a7
--- /dev/null
+++ b/testsuite/synth/if03/tb_if01.vhdl
@@ -0,0 +1,58 @@
+entity tb_if01 is
+end tb_if01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_if01 is
+ signal a : std_logic;
+ signal b : std_logic;
+ signal en1 : std_logic;
+ signal sel1 : std_logic;
+ signal clk : std_logic;
+ signal s1 : std_logic;
+ signal s2 : std_logic;
+begin
+ dut: entity work.if01
+ port map (
+ a => a,
+ b => b,
+ en1 => en1,
+ sel1 => sel1,
+ clk => clk,
+ s1 => s1,
+ s2 => s2);
+
+ process
+ procedure pulse is
+ begin
+ clk <= '0';
+ wait for 1 ns;
+ clk <= '1';
+ wait for 1 ns;
+ end pulse;
+ begin
+ en1 <= '1';
+ b <= '1';
+ a <= '0';
+ pulse;
+ assert s1 = '0' severity failure;
+ assert s2 = '1' severity failure;
+
+ en1 <= '1';
+ b <= '0';
+ a <= '1';
+ pulse;
+ assert s1 = '1' severity failure;
+ assert s2 = '0' severity failure;
+
+ en1 <= '0';
+ b <= 'X';
+ a <= 'X';
+ pulse;
+ assert s1 = '1' severity failure;
+ assert s2 = '0' severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/if03/testsuite.sh b/testsuite/synth/if03/testsuite.sh
new file mode 100755
index 000000000..5b9962346
--- /dev/null
+++ b/testsuite/synth/if03/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_tb if01
+
+echo "Test successful"