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authorTristan Gingold <tgingold@free.fr>2018-01-11 06:50:29 +0100
committerTristan Gingold <tgingold@free.fr>2018-01-11 12:51:48 +0100
commit89a7a47d3d611953063a850e521d1a466a8c1e80 (patch)
treec9b4439a4436fadbb90da272b84fbb7e70634a42 /testsuite
parent1f5df6e6262b6f01ca51b9bd1fefe9d8e2ba7308 (diff)
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Add testcase for previous commit.
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/gna/bug084/func_test1.vhdl58
-rw-r--r--testsuite/gna/bug084/func_test2.vhdl49
-rw-r--r--testsuite/gna/bug084/func_test3.vhdl28
-rw-r--r--testsuite/gna/bug084/mod5.vhdl137
-rw-r--r--testsuite/gna/bug084/mod5x.vhdl150
-rwxr-xr-xtestsuite/gna/bug084/testsuite.sh22
6 files changed, 444 insertions, 0 deletions
diff --git a/testsuite/gna/bug084/func_test1.vhdl b/testsuite/gna/bug084/func_test1.vhdl
new file mode 100644
index 000000000..20a5c97ef
--- /dev/null
+++ b/testsuite/gna/bug084/func_test1.vhdl
@@ -0,0 +1,58 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package subp_type_decl is
+ constant NBITS: natural := 6;
+ function mod5 (dividend: std_logic_vector) return std_logic;
+end package;
+package body subp_type_decl is
+ function mod5 (dividend: std_logic_vector) return std_logic is
+ type remains is (r0, r1, r2, r3, r4); -- remainder values
+ type remain_array is array (NBITS downto 0) of remains;
+ type branch is array (remains, bit) of remains;
+ constant br_table: branch := ( r0 => ('0' => r0, '1' => r1),
+ r1 => ('0' => r2, '1' => r3),
+ r2 => ('0' => r4, '1' => r0),
+ r3 => ('0' => r1, '1' => r2),
+ r4 => ('0' => r3, '1' => r4)
+ );
+ variable remaind: remain_array := (others => r0);
+ variable tbit: bit_vector (NBITS - 1 downto 0);
+ begin
+ tbit := to_bitvector(dividend); -- little endian
+ for i in dividend'length - 1 downto 0 loop
+ remaind(i) := br_table(remaind(i + 1),tbit(i));
+ end loop;
+ if remaind(0) = r0 then
+ return '1';
+ else
+ return '0';
+ end if;
+ end function;
+end package body;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.subp_type_decl.all;
+
+entity func_test1 is
+end entity;
+
+architecture fum of func_test1 is
+ signal dividend: std_logic_vector (NBITS - 1 downto 0);
+begin
+ process
+ variable errors: natural;
+ begin
+ errors := 0;
+ for i in 0 to 2 ** NBITS - 1 loop
+ dividend <= std_logic_vector(to_unsigned(i, NBITS));
+ wait for 0 ns;
+ report "mod5 (" & integer'image(i) & ") = " &
+ std_ulogic'image(mod5(dividend));
+ end loop;
+ wait;
+ end process;
+end architecture;
+
diff --git a/testsuite/gna/bug084/func_test2.vhdl b/testsuite/gna/bug084/func_test2.vhdl
new file mode 100644
index 000000000..b8e48b781
--- /dev/null
+++ b/testsuite/gna/bug084/func_test2.vhdl
@@ -0,0 +1,49 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity func_test2 is
+ generic (NBITS: natural := 6);
+end entity;
+
+architecture fum of func_test2 is
+ signal dividend: std_logic_vector (NBITS - 1 downto 0);
+
+ function mod5 (dividend: std_logic_vector) return std_logic is
+ type remains is (r0, r1, r2, r3, r4); -- remainder values
+ type remain_array is array (NBITS downto 0) of remains;
+ type branch is array (remains, bit) of remains;
+ constant br_table: branch := ( r0 => ('0' => r0, '1' => r1),
+ r1 => ('0' => r2, '1' => r3),
+ r2 => ('0' => r4, '1' => r0),
+ r3 => ('0' => r1, '1' => r2),
+ r4 => ('0' => r3, '1' => r4)
+ );
+ variable remaind: remain_array := (others => r0);
+ variable tbit: bit_vector (NBITS - 1 downto 0);
+ begin
+ tbit := to_bitvector(dividend); -- little endian
+ for i in dividend'length - 1 downto 0 loop
+ remaind(i) := br_table(remaind(i + 1),tbit(i));
+ end loop;
+ if remaind(0) = r0 then
+ return '1';
+ else
+ return '0';
+ end if;
+ end function;
+begin
+ process
+ variable errors: natural;
+ begin
+ errors := 0;
+ for i in 0 to 2 ** NBITS - 1 loop
+ dividend <= std_logic_vector(to_unsigned(i, NBITS));
+ wait for 0 ns;
+ report "mod5(" & integer'image(i) &") = " &
+ std_ulogic'image(mod5(dividend));
+ end loop;
+ wait;
+ end process;
+end architecture;
+
diff --git a/testsuite/gna/bug084/func_test3.vhdl b/testsuite/gna/bug084/func_test3.vhdl
new file mode 100644
index 000000000..1dd74dd7b
--- /dev/null
+++ b/testsuite/gna/bug084/func_test3.vhdl
@@ -0,0 +1,28 @@
+entity func_test3 is
+ generic (NBITS: natural := 6);
+end entity;
+
+architecture fum of func_test3 is
+ type remains is (r0, r1, r2, r3, r4); -- remainder values
+
+ function mod5 (dividend: bit_vector) return boolean is
+ type remain_array is array (NBITS downto 0) of remains;
+ type branch is array (remains, bit) of remains;
+ constant br_table: branch := ( r0 => ('0' => r0, '1' => r1),
+ r1 => ('0' => r2, '1' => r3),
+ r2 => ('0' => r4, '1' => r0),
+ r3 => ('0' => r1, '1' => r2),
+ r4 => ('0' => r3, '1' => r4)
+ );
+ variable remaind: remains := r0;
+ variable tbit: bit_vector (NBITS - 1 downto 0) := dividend;
+ begin
+ for i in dividend'length - 1 downto 0 loop
+ remaind := br_table(remaind,tbit(i));
+ end loop;
+ return remaind = r0;
+ end function;
+begin
+ assert mod5("101000");
+end architecture;
+
diff --git a/testsuite/gna/bug084/mod5.vhdl b/testsuite/gna/bug084/mod5.vhdl
new file mode 100644
index 000000000..57ee1819d
--- /dev/null
+++ b/testsuite/gna/bug084/mod5.vhdl
@@ -0,0 +1,137 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity mod5 is
+ generic (
+ NBITS: natural := 13
+ );
+ port (
+ clk: in std_logic;
+ dividend: in std_logic_vector (NBITS - 1 downto 0);
+ load: in std_logic;
+ remzero: out std_logic
+ );
+end entity;
+
+architecture foo of mod5 is
+ type remains is (r0, r1, r2, r3, r4); -- remainder values
+ type remain_array is array (NBITS downto 0) of remains;
+ signal remaindr: remain_array := (others => r0);
+ type branch is array (remains, bit) of remains;
+-- Dave Tweeds state transition table:
+ constant br_table: branch := ( r0 => ('0' => r0, '1' => r1),
+ r1 => ('0' => r2, '1' => r3),
+ r2 => ('0' => r4, '1' => r0),
+ r3 => ('0' => r1, '1' => r2),
+ r4 => ('0' => r3, '1' => r4)
+ );
+begin
+
+do_ig:
+ process (dividend)
+ variable tbit: bit_vector(NBITS - 1 downto 0);
+ variable remaind: remain_array := (others => r0);
+ begin
+do_mod:
+ for i in NBITS - 1 downto 0 loop
+ tbit := to_bitvector(dividend);
+ remaind(i) := br_table(remaind(i + 1),tbit(i));
+ end loop;
+ remaindr <= remaind; -- all values for waveform display
+ end process;
+
+remainders:
+ process (clk)
+ begin
+ if rising_edge(clk) then
+ if remaindr(0) = r0 then
+ remzero <= '1';
+ else
+ remzero <= '0';
+ end if;
+ end if;
+ end process;
+end architecture;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity mod5_tb is
+end entity;
+
+architecture foo of mod5_tb is
+ constant NBITS: integer range 0 to 13 := 8;
+ signal clk: std_logic := '0';
+ signal dividend: std_logic_vector (NBITS - 1 downto 0);
+ signal load: std_logic := '0';
+
+ signal remzero: std_logic;
+
+ signal psample: std_ulogic;
+ signal sample: std_ulogic;
+ signal done: boolean;
+begin
+DUT:
+ entity work.mod5
+ generic map (NBITS)
+ port map (
+ clk => clk,
+ dividend => dividend,
+ load => load,
+ remzero => remzero
+ );
+CLOCK:
+ process
+ begin
+ wait for 5 ns;
+ clk <= not clk;
+ if done'delayed(30 ns) then
+ wait;
+ end if;
+ end process;
+STIMULI:
+ process
+ begin
+ for i in 0 to 2 ** NBITS - 1 loop
+ wait for 10 ns;
+ dividend <= std_logic_vector(to_unsigned(i,NBITS));
+ wait for 10 ns;
+ load <= '1';
+ wait for 10 ns;
+ load <= '0';
+ end loop;
+ wait for 15 ns;
+ done <= true;
+ wait;
+ end process;
+
+SAMPLER:
+ process (clk)
+ begin
+ if rising_edge(clk) then
+ psample <= load;
+ sample <= psample;
+ end if;
+ end process;
+
+MONITOR:
+ process (sample)
+ variable i: integer;
+ variable rem5: integer;
+ begin
+ if rising_edge (sample) then
+ i := to_integer(unsigned(dividend));
+ rem5 := i mod 5;
+ if rem5 = 0 and remzero /= '1' then
+ assert rem5 = 0 and remzero = '1'
+ report LF & HT &
+ "i = " & integer'image(i) &
+ " rem 5 expected " & integer'image(rem5) &
+ " remzero = " & std_ulogic'image(remzero)
+ SEVERITY ERROR;
+ end if;
+ end if;
+ end process;
+
+end architecture; \ No newline at end of file
diff --git a/testsuite/gna/bug084/mod5x.vhdl b/testsuite/gna/bug084/mod5x.vhdl
new file mode 100644
index 000000000..9a4d4a6cd
--- /dev/null
+++ b/testsuite/gna/bug084/mod5x.vhdl
@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity mod5x is
+ generic (
+ NBITS: natural := 13
+ );
+ port (
+ clk: in std_logic;
+ dividend: in std_logic_vector (NBITS - 1 downto 0);
+ load: in std_logic;
+ remzero: out std_logic
+ );
+end entity;
+
+architecture foo of mod5x is
+ -- type remains is (r0, r1, r2, r3, r4); -- remainder values
+ -- type remain_array is array (NBITS downto 0) of remains;
+ -- signal remaindr: remain_array := (others => r0);
+-- type branch is array (remains, bit) of remains;
+-- -- Dave Tweeds state transition table:
+-- constant br_table: branch := ( r0 => ('0' => r0, '1' => r1),
+-- r1 => ('0' => r2, '1' => r3),
+-- r2 => ('0' => r4, '1' => r0),
+-- r3 => ('0' => r1, '1' => r2),
+-- r4 => ('0' => r3, '1' => r4)
+-- );
+ signal is_zero: std_logic;
+begin
+
+do_ig:
+ process (dividend)
+ type remains is (r0, r1, r2, r3, r4); -- remainder values
+ type remain_array is array (NBITS downto 0) of remains;
+ variable tbit: bit_vector(NBITS - 1 downto 0);
+ variable remaind: remain_array := (others => r0);
+ type branch is array (remains, bit) of remains;
+ -- Dave Tweeds state transition table:
+ constant br_table: branch := ( r0 => ('0' => r0, '1' => r1),
+ r1 => ('0' => r2, '1' => r3),
+ r2 => ('0' => r4, '1' => r0),
+ r3 => ('0' => r1, '1' => r2),
+ r4 => ('0' => r3, '1' => r4)
+ );
+ begin
+do_mod:
+ for i in NBITS - 1 downto 0 loop
+ tbit := to_bitvector(dividend);
+ remaind(i) := br_table(remaind(i + 1),tbit(i));
+ end loop;
+ -- remaindr <= remaind; -- all values for waveform display
+ if remaind(0) = r0 then
+ is_zero <= '1';
+ else
+ is_zero <= '0';
+ end if;
+ end process;
+
+remainders:
+ process (clk)
+ begin
+ if rising_edge(clk) then
+ remzero <= is_zero
+ ;
+ end if;
+ end process;
+end architecture;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity mod5x_tb is
+end entity;
+
+architecture foo of mod5x_tb is
+ constant NBITS: integer range 0 to 13 := 8;
+ signal clk: std_logic := '0';
+ signal dividend: std_logic_vector (NBITS - 1 downto 0);
+ signal load: std_logic := '0';
+
+ signal remzero: std_logic;
+
+ signal psample: std_ulogic;
+ signal sample: std_ulogic;
+ signal done: boolean;
+begin
+DUT:
+ entity work.mod5x
+ generic map (NBITS)
+ port map (
+ clk => clk,
+ dividend => dividend,
+ load => load,
+ remzero => remzero
+ );
+CLOCK:
+ process
+ begin
+ wait for 5 ns;
+ clk <= not clk;
+ if done'delayed(30 ns) then
+ wait;
+ end if;
+ end process;
+STIMULI:
+ process
+ begin
+ for i in 0 to 2 ** NBITS - 1 loop
+ wait for 10 ns;
+ dividend <= std_logic_vector(to_unsigned(i,NBITS));
+ wait for 10 ns;
+ load <= '1';
+ wait for 10 ns;
+ load <= '0';
+ end loop;
+ wait for 15 ns;
+ done <= true;
+ wait;
+ end process;
+
+SAMPLER:
+ process (clk)
+ begin
+ if rising_edge(clk) then
+ psample <= load;
+ sample <= psample;
+ end if;
+ end process;
+
+MONITOR:
+ process (sample)
+ variable i: integer;
+ variable rem5: integer;
+ begin
+ if rising_edge (sample) then
+ i := to_integer(unsigned(dividend));
+ rem5 := i mod 5;
+ if rem5 = 0 and remzero /= '1' then
+ assert rem5 = 0 and remzero = '1'
+ report LF & HT &
+ "i = " & integer'image(i) &
+ " rem 5 expected " & integer'image(rem5) &
+ " remzero = " & std_ulogic'image(remzero)
+ SEVERITY ERROR;
+ end if;
+ end if;
+ end process;
+
+end architecture; \ No newline at end of file
diff --git a/testsuite/gna/bug084/testsuite.sh b/testsuite/gna/bug084/testsuite.sh
new file mode 100755
index 000000000..5d8d18895
--- /dev/null
+++ b/testsuite/gna/bug084/testsuite.sh
@@ -0,0 +1,22 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze func_test3.vhdl
+elab_simulate func_test3
+
+analyze func_test1.vhdl
+elab_simulate func_test1
+
+analyze func_test2.vhdl
+elab_simulate func_test2
+
+analyze mod5.vhdl
+elab_simulate mod5_tb
+
+analyze mod5x.vhdl
+elab_simulate mod5x_tb
+
+clean
+
+echo "Test successful"