testsuite/synth: add test for #1197

2 files changed, 55 insertions, 0 deletions

diff --git a/testsuite/synth/issue1197/generics_1.vhdl b/testsuite/synth/issue1197/generics_1.vhdl
new file mode 100644
index 000000000..197e2656a
--- /dev/null
+++ b/testsuite/synth/issue1197/generics_1.vhdl
@@ -0,0 +1,46 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+entity addern is
+ generic(
+  width : integer := 8
+ );
+ port(
+  A, B : in  std_logic_vector(width - 1 downto 0);
+  Y    : out std_logic_vector(width - 1 downto 0)
+ );
+end addern;
+
+architecture bhv of addern is
+begin
+ Y <= A + B;
+end bhv;
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity generics_1 is
+ port(
+  X, Y, Z : in  std_logic_vector(12 downto 0);
+  A, B    : in  std_logic_vector(4 downto 0);
+  S       : out std_logic_vector(17 downto 0));
+end generics_1;
+
+architecture bhv of generics_1 is
+ component addern
+  generic(width : integer := 8);
+  port(
+   A, B : in  std_logic_vector(width - 1 downto 0);
+   Y    : out std_logic_vector(width - 1 downto 0));
+ end component;
+ for all : addern use entity work.addern(bhv);
+
+ signal C1     : std_logic_vector(12 downto 0);
+ signal C2, C3 : std_logic_vector(17 downto 0);
+begin
+ U1 : addern generic map(width => 13) port map(X, Y, C1);
+ C2 <= C1 & A;
+ C3 <= Z & B;
+ U2 : addern generic map(width => 18) port map(C2, C3, S);
+end bhv;
diff --git a/testsuite/synth/issue1197/testsuite.sh b/testsuite/synth/issue1197/testsuite.sh
new file mode 100755
index 000000000..e8d483a35
--- /dev/null
+++ b/testsuite/synth/issue1197/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=-fsynopsys
+synth_analyze generics_1
+clean
+
+echo "Test successful"