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| author | Tristan Gingold <tgingold@free.fr> | 2020-03-23 07:29:33 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-03-23 07:29:33 +0100 |
| commit | 7e6fc375fcd573489204fbda6cddb863d6a132cc (patch) | |
| tree | 7812ff6b2b9fbb3d68884ea7449339eb40e35a1f /testsuite | |
| parent | d69e4db4db55c0d5eb549a6554ae0ab6840fcde2 (diff) | |
| download | ghdl-7e6fc375fcd573489204fbda6cddb863d6a132cc.tar.gz ghdl-7e6fc375fcd573489204fbda6cddb863d6a132cc.tar.bz2 ghdl-7e6fc375fcd573489204fbda6cddb863d6a132cc.zip | |
testsuite/synth: add a test for #1170
Diffstat (limited to 'testsuite')
| -rw-r--r-- | testsuite/synth/issue1170/bug.vhdl | 20 | ||||
| -rwxr-xr-x | testsuite/synth/issue1170/testsuite.sh | 8 |
2 files changed, 28 insertions, 0 deletions
diff --git a/testsuite/synth/issue1170/bug.vhdl b/testsuite/synth/issue1170/bug.vhdl new file mode 100644 index 000000000..d68ad2beb --- /dev/null +++ b/testsuite/synth/issue1170/bug.vhdl @@ -0,0 +1,20 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity bug is + port( + dummy : in std_ulogic + ); +end bug; + +architecture behav of bug is + constant LEN : positive := 2; +begin + outer : block + begin + gen : for i in 0 to LEN-1 generate + --empty + end generate; + end block; +end architecture; diff --git a/testsuite/synth/issue1170/testsuite.sh b/testsuite/synth/issue1170/testsuite.sh new file mode 100755 index 000000000..121ca9a6a --- /dev/null +++ b/testsuite/synth/issue1170/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +synth_analyze bug +clean + +echo "Test successful" |