testsuite/gna: add a test for #2299

3 files changed, 61 insertions, 0 deletions

diff --git a/testsuite/gna/issue2299/tb_dct.vhdl b/testsuite/gna/issue2299/tb_dct.vhdl
new file mode 100644
index 000000000..35c16327e
--- /dev/null
+++ b/testsuite/gna/issue2299/tb_dct.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+entity tb_dct8 is
+end tb_dct8;
+
+architecture beh of tb_dct8 is
+    signal r : real;
+begin
+    process
+        variable line0 : line;
+    begin
+        r <= 123.0;
+        write(line0, to_string(r, 8));
+        writeline(output, line0);
+        wait;
+    end process;
+end architecture;
diff --git a/testsuite/gna/issue2299/tb_dct8.vhdl b/testsuite/gna/issue2299/tb_dct8.vhdl
new file mode 100644
index 000000000..eb63d1ff7
--- /dev/null
+++ b/testsuite/gna/issue2299/tb_dct8.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+entity tb_dct8 is
+end tb_dct8;
+
+architecture beh of tb_dct8 is
+    procedure write_arr(x : real_vector) is
+        variable line0 : line;
+    begin
+        for n in x'range loop
+            write(line0, to_string(x(n), 4), right, 5);
+            write(line0, string'(" "));
+        end loop;
+        writeline(output, line0);
+    end procedure;
+    signal y : real_vector(0 to 7);
+begin
+    process
+    begin
+        write_arr(y);
+        assert false report "all tests passed" severity note;
+        wait;
+    end process;
+end architecture;
diff --git a/testsuite/gna/issue2299/testsuite.sh b/testsuite/gna/issue2299/testsuite.sh
new file mode 100755
index 000000000..cc285234c
--- /dev/null
+++ b/testsuite/gna/issue2299/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze tb_dct8.vhdl
+elab_simulate tb_dct8
+
+analyze tb_dct.vhdl
+elab_simulate tb_dct8
+
+clean
+
+echo "Test successful"