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authorTristan Gingold <tgingold@free.fr>2022-08-14 09:47:43 +0200
committerTristan Gingold <tgingold@free.fr>2022-08-14 20:53:50 +0200
commit73256b07e3884622e1c8e3cce4b958e26dd3beb5 (patch)
tree4b2d590582cad724bf47876853538f61c3194f50 /testsuite
parent11a8554f828436d78e1a01c683219bef4d83db97 (diff)
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testsuite/synth: add a test for #2176
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/synth/issue2176/math_real_test.vhdl23
-rwxr-xr-xtestsuite/synth/issue2176/testsuite.sh7
2 files changed, 30 insertions, 0 deletions
diff --git a/testsuite/synth/issue2176/math_real_test.vhdl b/testsuite/synth/issue2176/math_real_test.vhdl
new file mode 100644
index 000000000..61223d64a
--- /dev/null
+++ b/testsuite/synth/issue2176/math_real_test.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+library work;
+
+entity math_real_test is
+ port
+ (
+ dout : out std_logic_vector(15 downto 0)
+ );
+end math_real_test;
+
+architecture rtl of math_real_test is
+
+ signal threshold : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(integer(floor(log10(sqrt(4096.0 * MATH_SQRT_PI)))), 16));
+
+begin
+
+ dout <= threshold;
+
+end;
diff --git a/testsuite/synth/issue2176/testsuite.sh b/testsuite/synth/issue2176/testsuite.sh
new file mode 100755
index 000000000..1aa58681f
--- /dev/null
+++ b/testsuite/synth/issue2176/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_only math_real_test
+
+echo "Test successful"