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author | Tristan Gingold <tgingold@free.fr> | 2019-11-09 21:52:04 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-11-11 20:28:31 +0100 |
commit | 72094d312400368dda79e32b4403d0f142404fad (patch) | |
tree | 86406d805a60ec7131fd4d06d68865103d187014 /testsuite | |
parent | 81254216c4e8ba25ff98b3c77f7beb0f834d1a27 (diff) | |
download | ghdl-72094d312400368dda79e32b4403d0f142404fad.tar.gz ghdl-72094d312400368dda79e32b4403d0f142404fad.tar.bz2 ghdl-72094d312400368dda79e32b4403d0f142404fad.zip |
testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/synth/memmux01/memmux07.vhdl | 23 | ||||
-rw-r--r-- | testsuite/synth/memmux01/tb_memmux07.vhdl | 51 | ||||
-rwxr-xr-x | testsuite/synth/memmux01/testsuite.sh | 2 |
3 files changed, 75 insertions, 1 deletions
diff --git a/testsuite/synth/memmux01/memmux07.vhdl b/testsuite/synth/memmux01/memmux07.vhdl new file mode 100644 index 000000000..f408aa338 --- /dev/null +++ b/testsuite/synth/memmux01/memmux07.vhdl @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity memmux07 is + port (ad : std_logic; + val : std_logic_vector (1 downto 0); + dat : std_logic_vector (7 downto 0); + res : out std_logic_vector (7 downto 0)); +end memmux07; + +architecture behav of memmux07 is +begin + process (ad, val, dat) + variable lo : natural; + variable t : std_logic_vector(7 downto 0); + begin + lo := to_integer(unsigned'(0 => ad)); + t := dat; + t (4 * lo + 1 downto 4 * lo) := val; + res <= t; + end process; +end behav; diff --git a/testsuite/synth/memmux01/tb_memmux07.vhdl b/testsuite/synth/memmux01/tb_memmux07.vhdl new file mode 100644 index 000000000..3efee65bc --- /dev/null +++ b/testsuite/synth/memmux01/tb_memmux07.vhdl @@ -0,0 +1,51 @@ +entity tb_memmux07 is +end tb_memmux07; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +architecture behav of tb_memmux07 is + signal ad : std_logic; + signal val : std_logic_vector (1 downto 0); + signal dat, res : std_logic_vector (7 downto 0); +begin + dut : entity work.memmux07 + port map ( + ad => ad, + val => val, + dat => dat, + res => res); + + process + begin + dat <= x"de"; + + ad <= '0'; + val <= "00"; + wait for 1 ns; + assert res = x"dc" severity failure; + + ad <= '1'; + val <= "00"; + wait for 1 ns; + assert res = x"ce" severity failure; + + ad <= '0'; + val <= "01"; + wait for 1 ns; + assert res = x"dd" severity failure; + + ad <= '0'; + val <= "10"; + wait for 1 ns; + assert res = x"de" severity failure; + + ad <= '1'; + val <= "10"; + wait for 1 ns; + assert res = x"ee" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/memmux01/testsuite.sh b/testsuite/synth/memmux01/testsuite.sh index d42d27482..7a9179100 100755 --- a/testsuite/synth/memmux01/testsuite.sh +++ b/testsuite/synth/memmux01/testsuite.sh @@ -3,7 +3,7 @@ . ../../testenv.sh GHDL_STD_FLAGS=--std=08 -for t in memmux01 memmux02 memmux03 memmux04 memmux05; do +for t in memmux01 memmux02 memmux03 memmux04 memmux05 memmux07; do analyze $t.vhdl tb_$t.vhdl elab_simulate tb_$t clean |