testsuite/synth: add test for previous commit.

4 files changed, 99 insertions, 0 deletions

diff --git a/testsuite/synth/rec01/pkg_rec01.vhdl b/testsuite/synth/rec01/pkg_rec01.vhdl
new file mode 100644
index 000000000..ecf0006ed
--- /dev/null
+++ b/testsuite/synth/rec01/pkg_rec01.vhdl
@@ -0,0 +1,10 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package rec01_pkg is
+  type myrec is record
+     a : unsigned (3 downto 0);
+     b : std_logic;
+  end record;
+end rec01_pkg;
diff --git a/testsuite/synth/rec01/rec01.vhdl b/testsuite/synth/rec01/rec01.vhdl
new file mode 100644
index 000000000..e5eb86048
--- /dev/null
+++ b/testsuite/synth/rec01/rec01.vhdl
@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec01_pkg.all;
+
+entity rec01 is
+  port (inp : myrec;
+        rst : std_logic;
+        clk : std_logic;
+        o : out std_logic);
+end rec01;
+
+architecture behav of rec01 is
+  signal s : myrec;
+begin
+  process (clk) is
+  begin
+    if rising_edge (clk) then
+      if rst = '1' then
+        s <= (a => "0000", b => '0');
+      else
+        if inp.b = '1' then
+          s <= (a => inp.a, b => '1');
+        else
+          s <= inp;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  o <= '1' when s.a (1) = s.b else '0';
+end behav;
diff --git a/testsuite/synth/rec01/tb_rec01.vhdl b/testsuite/synth/rec01/tb_rec01.vhdl
new file mode 100644
index 000000000..da9e0ff38
--- /dev/null
+++ b/testsuite/synth/rec01/tb_rec01.vhdl
@@ -0,0 +1,42 @@
+entity tb_rec01 is
+end tb_rec01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec01_pkg.all;
+
+architecture behav of tb_rec01 is
+  signal inp : myrec;
+  signal clk : std_logic;
+  signal rst : std_logic;
+  signal r : std_logic;
+begin
+  dut: entity work.rec01
+    port map (inp => inp, clk => clk, rst => rst, o => r);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    rst <= '1';
+    pulse;
+    assert r = '1' severity failure;
+
+    rst <= '0';
+    inp <= (a => "0010", b => '1');
+    pulse;
+    assert r = '1' severity failure;
+
+    rst <= '0';
+    inp <= (a => "0001", b => '1');
+    pulse;
+    assert r = '0' severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/rec01/testsuite.sh b/testsuite/synth/rec01/testsuite.sh
new file mode 100755
index 000000000..dcb0aba24
--- /dev/null
+++ b/testsuite/synth/rec01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in rec01; do
+    analyze pkg_$t.vhdl $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth pkg_$t.vhdl $t.vhdl -e $t > syn_$t.vhdl
+    analyze pkg_$t.vhdl syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t --ieee-asserts=disable-at-0
+    clean
+done
+
+echo "Test successful"