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author | Tristan Gingold <tgingold@free.fr> | 2019-11-01 18:46:16 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-11-01 18:46:16 +0100 |
commit | 66b34c936b1ef472a532673bed0543287311e995 (patch) | |
tree | 37b82cb3ba3ae9238bbb8c52990f360a69a8c936 /testsuite | |
parent | a4b5dd0fb373bf785abfc1f6666ce8d6a32a6e08 (diff) | |
download | ghdl-66b34c936b1ef472a532673bed0543287311e995.tar.gz ghdl-66b34c936b1ef472a532673bed0543287311e995.tar.bz2 ghdl-66b34c936b1ef472a532673bed0543287311e995.zip |
testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/synth/forgen01/forgen03.vhdl | 38 | ||||
-rw-r--r-- | testsuite/synth/forgen01/tb_forgen03.vhdl | 29 | ||||
-rwxr-xr-x | testsuite/synth/forgen01/testsuite.sh | 2 |
3 files changed, 68 insertions, 1 deletions
diff --git a/testsuite/synth/forgen01/forgen03.vhdl b/testsuite/synth/forgen01/forgen03.vhdl new file mode 100644 index 000000000..1a4828302 --- /dev/null +++ b/testsuite/synth/forgen01/forgen03.vhdl @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity fulladder is + port (a, b, ci : std_logic; + o, co : out std_logic); +end fulladder; + +architecture behav of fulladder is +begin + o <= a xor b xor ci; + co <= (a and b) or (a and ci) or (b and ci); +end behav; + +library ieee; +use ieee.std_logic_1164.all; + +entity forgen03 is + generic (l : natural := 8; + structural : boolean := true); + port (a, b : std_logic_vector (l - 1 downto 0); + o : out std_logic_vector (l - 1 downto 0)); +end forgen03; + +architecture behav of forgen03 +is +begin + gstr: if structural generate + signal carry : std_logic_vector (l downto 0); + begin + carry (0) <= '0'; + gadd: for i in 0 to l - 1 generate + iadd: entity work.fulladder + port map (a => a (i), b => b (i), ci => carry (i), + o => o (i), co => carry (i + 1)); + end generate; + end generate; +end behav; diff --git a/testsuite/synth/forgen01/tb_forgen03.vhdl b/testsuite/synth/forgen01/tb_forgen03.vhdl new file mode 100644 index 000000000..d03046781 --- /dev/null +++ b/testsuite/synth/forgen01/tb_forgen03.vhdl @@ -0,0 +1,29 @@ +entity tb_forgen03 is +end tb_forgen03; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_forgen03 is + signal a : std_logic_vector (7 downto 0); + signal b : std_logic_vector (7 downto 0); + signal o : std_logic_vector (7 downto 0); +begin + dut: entity work.forgen03 + port map (a, b, o); + + process + begin + a <= x"30"; + b <= x"28"; + wait for 1 ns; + assert o = x"58" severity failure; + + a <= x"11"; + b <= x"f7"; + wait for 1 ns; + assert o = x"08" severity failure; + + wait; + end process; +end behav; diff --git a/testsuite/synth/forgen01/testsuite.sh b/testsuite/synth/forgen01/testsuite.sh index cbc0107c7..d9818a2e2 100755 --- a/testsuite/synth/forgen01/testsuite.sh +++ b/testsuite/synth/forgen01/testsuite.sh @@ -2,7 +2,7 @@ . ../../testenv.sh -for t in forgen01 forgen02; do +for t in forgen01 forgen02 forgen03; do analyze $t.vhdl tb_$t.vhdl elab_simulate tb_$t clean |