testsuite/gna: add a test for #887

3 files changed, 125 insertions, 0 deletions

diff --git a/testsuite/gna/issue887/test.vhdl b/testsuite/gna/issue887/test.vhdl
new file mode 100644
index 000000000..1178b597c
--- /dev/null
+++ b/testsuite/gna/issue887/test.vhdl
@@ -0,0 +1,58 @@
+library ieee;
+use ieee.fixed_float_types.all;
+use ieee.fixed_pkg.all;
+
+package filtPkg is
+  type u_sfixed_array is array (integer range <>) of u_sfixed;
+end package filtPkg;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.fixed_float_types.all;
+use ieee.fixed_pkg.all;
+use work.filtpkg.all;
+
+entity filter is
+  generic (
+    intbits_g: natural;
+    decbits_g: natural
+  );
+  port (
+    clk: in std_ulogic;
+    c: in u_sfixed_array
+  );
+end entity filter;
+
+architecture rtl of filter
+is
+  signal tmp: u_sfixed (intbits_g - 1 downto - decbits_g);
+begin
+  tmp <= c (0);
+end architecture rtl;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.fixed_float_types.all;
+use ieee.fixed_pkg.all;
+use work.filtpkg.all;
+
+entity tb is
+end entity tb;
+
+architecture test of tb
+is
+  constant intbits_c: natural := 4;
+  constant decbits_c: natural := 6;
+  signal clk: std_ulogic := '0';
+  signal done: boolean := false;
+  signal coeff: u_sfixed_array (0 to 5) (intbits_c - 1 downto - decbits_c) := (others => (others => '0'));
+  signal tmp: u_sfixed (intbits_c - 1 downto - decbits_c);
+begin
+  clk <= transport not clk after 10 ns when not done else '0';
+  done <= transport true after 500 ns;
+  tmp <= coeff (0);
+  filter_1: entity work.filter
+    generic map (intbits_g => intbits_c, decbits_g => decbits_c)
+    port map (clk => clk, c => coeff);
+end architecture test;
+
diff --git a/testsuite/gna/issue887/test2.vhdl b/testsuite/gna/issue887/test2.vhdl
new file mode 100644
index 000000000..afe3672aa
--- /dev/null
+++ b/testsuite/gna/issue887/test2.vhdl
@@ -0,0 +1,53 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package filtPkg2 is
+  type std_logic_vector_array is array (integer range <>) of std_logic_vector;
+end package filtPkg2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.filtpkg2.all;
+
+entity filter2 is
+  generic (
+    high_g: natural;
+    low_g: natural
+  );
+  port (
+    clk: in std_ulogic;
+    c: in std_logic_vector_array
+  );
+end entity filter2;
+
+architecture rtl of filter2
+is
+  signal tmp: std_logic_vector (high_g downto low_g);
+begin
+  tmp <= c (0);
+end architecture rtl;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.filtpkg2.all;
+
+entity tb2 is
+end entity tb2;
+
+architecture test of tb2
+is
+  constant high_c: natural := 7;
+  constant low_c: natural := 0;
+  signal clk: std_ulogic := '0';
+  signal done: boolean := false;
+  signal coeff: std_logic_vector_array (0 to 5) (high_c downto low_c) := (others => (others => '0'));
+  signal tmp: std_logic_vector (high_c downto low_c);
+begin
+  clk <= transport not clk after 10 ns when not done else '0';
+  done <= transport true after 500 ns;
+  tmp <= coeff (0);
+  filter2_1: entity work.filter2
+    generic map (high_g => high_c, low_g => low_c)
+    port map (clk => clk, c => coeff);
+end architecture test;
+
diff --git a/testsuite/gna/issue887/testsuite.sh b/testsuite/gna/issue887/testsuite.sh
new file mode 100755
index 000000000..34a016ec3
--- /dev/null
+++ b/testsuite/gna/issue887/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze test2.vhdl
+elab_simulate tb2
+
+analyze test.vhdl
+elab_simulate tb
+
+clean
+
+echo "Test successful"