Add reproducer for #687

6 files changed, 217 insertions, 0 deletions

diff --git a/testsuite/gna/issue687/ent.vhdl b/testsuite/gna/issue687/ent.vhdl
new file mode 100644
index 000000000..d19adae28
--- /dev/null
+++ b/testsuite/gna/issue687/ent.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+entity dut is
+	port (
+		sig_i : in std_logic_vector;
+		sig_o : out std_logic_vector
+	);
+end entity;
+architecture arch of dut is
+begin
+	sig_o <= sig_i;
+end architecture;
+
+library ieee;
+use ieee.std_logic_1164.all;
+entity tb is
+end entity;
+architecture bench of tb is
+	signal sin : std_ulogic_vector(1 downto 0);
+	signal sout : std_ulogic_vector(31 downto 0);
+begin
+	stim : process
+	begin
+		wait for 1 ns;
+		report to_string(sin);
+		report to_string(sout);
+		std.env.finish;
+	end process;
+	dut_inst: entity work.dut port map (
+		sig_i => sin,
+		sig_o => sout
+	);
+end architecture;
diff --git a/testsuite/gna/issue687/ent2.vhdl b/testsuite/gna/issue687/ent2.vhdl
new file mode 100644
index 000000000..cabbee641
--- /dev/null
+++ b/testsuite/gna/issue687/ent2.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+entity dut is
+	port (
+		sig_i : in std_logic_vector;
+		sig_o : out std_logic_vector
+	);
+end entity;
+architecture arch of dut is
+begin
+	sig_o <= sig_i after 1 ns;
+end architecture;
+
+library ieee;
+use ieee.std_logic_1164.all;
+entity tb is
+end entity;
+architecture bench of tb is
+	signal sin : std_ulogic_vector(1 downto 0);
+	signal sout : std_ulogic_vector(31 downto 0);
+begin
+	stim : process
+	begin
+		wait for 1 ns;
+		report to_string(sin);
+		report to_string(sout);
+		std.env.finish;
+	end process;
+	dut_inst: entity work.dut port map (
+		sig_i => sin,
+		sig_o => sout
+	);
+end architecture;
diff --git a/testsuite/gna/issue687/ent3.vhdl b/testsuite/gna/issue687/ent3.vhdl
new file mode 100644
index 000000000..25ff9c3ae
--- /dev/null
+++ b/testsuite/gna/issue687/ent3.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+entity dut is
+	port (
+		sig_i : in std_logic_vector;
+		sig_o : out std_logic_vector
+	);
+end entity;
+architecture arch of dut is
+begin
+	sig_o <= (sig_o'range => 'X') after 1 ns, sig_i after 2 ns;
+end architecture;
+
+library ieee;
+use ieee.std_logic_1164.all;
+entity tb is
+end entity;
+architecture bench of tb is
+	signal sin : std_ulogic_vector(1 downto 0);
+	signal sout : std_ulogic_vector(31 downto 0);
+begin
+	stim : process
+	begin
+		wait for 3 ns;
+		report to_string(sin);
+		report to_string(sout);
+		std.env.finish;
+	end process;
+	dut_inst: entity work.dut port map (
+		sig_i => sin,
+		sig_o => sout
+	);
+end architecture;
diff --git a/testsuite/gna/issue687/ent4.vhdl b/testsuite/gna/issue687/ent4.vhdl
new file mode 100644
index 000000000..6b3501a18
--- /dev/null
+++ b/testsuite/gna/issue687/ent4.vhdl
@@ -0,0 +1,39 @@
+library ieee;
+use ieee.std_logic_1164.all;
+entity dut is
+	port (
+		sig_i : in std_logic_vector;
+		sig_o : out std_logic_vector
+	);
+end entity;
+architecture arch of dut is
+begin
+  process
+  begin
+    sig_o <= sig_i;
+    report "not expected" severity note;
+    sig_o(1) <= '1' after 1 ns;
+    wait;
+  end process;
+end architecture;
+
+library ieee;
+use ieee.std_logic_1164.all;
+entity tb is
+end entity;
+architecture bench of tb is
+	signal sin : std_ulogic_vector(1 downto 0);
+	signal sout : std_ulogic_vector(31 downto 0);
+begin
+	stim : process
+	begin
+		wait for 3 ns;
+		report to_string(sin);
+		report to_string(sout);
+		std.env.finish;
+	end process;
+	dut_inst: entity work.dut port map (
+		sig_i => sin,
+		sig_o => sout
+	);
+end architecture;
diff --git a/testsuite/gna/issue687/ent_ok.vhdl b/testsuite/gna/issue687/ent_ok.vhdl
new file mode 100644
index 000000000..12b544cab
--- /dev/null
+++ b/testsuite/gna/issue687/ent_ok.vhdl
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+entity dut is
+	port (
+		sig_i : in std_logic_vector;
+		sig_o : out std_logic_vector
+	);
+end entity;
+architecture arch of dut is
+begin
+	sig_o <= sig_i;
+end architecture;
+
+library ieee;
+use ieee.std_logic_1164.all;
+entity tb is
+end entity;
+architecture bench of tb is
+	signal sin : std_ulogic_vector(31 downto 0);
+	signal sout : std_ulogic_vector(31 downto 0);
+begin
+	stim : process
+	begin
+		wait for 1 ns;
+		report to_string(sin);
+		report to_string(sout);
+		std.env.finish;
+	end process;
+	dut_inst: entity work.dut port map (
+		sig_i => sin,
+		sig_o => sout
+	);
+end architecture;
diff --git a/testsuite/gna/issue687/testsuite.sh b/testsuite/gna/issue687/testsuite.sh
new file mode 100755
index 000000000..2c71a7534
--- /dev/null
+++ b/testsuite/gna/issue687/testsuite.sh
@@ -0,0 +1,46 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+
+check_output()
+{
+    if ! grep -q "bound check failure" $1; then
+	echo "missing bound check failure"
+	exit 1
+    fi
+}
+
+analyze ent.vhdl
+elab_simulate_failure tb > tb.err
+check_output tb.err
+
+clean
+
+analyze ent_ok.vhdl
+elab_simulate tb
+
+clean
+
+analyze ent2.vhdl
+elab_simulate_failure tb > tb.err
+check_output tb.err
+
+clean
+
+analyze ent3.vhdl
+elab_simulate_failure tb > tb.err
+check_output tb.err
+
+clean
+
+analyze ent4.vhdl
+elab_simulate_failure tb > tb.err
+check_output tb.err
+
+clean
+
+rm -f tb.err
+
+echo "Test successful"