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author | Tristan Gingold <tgingold@free.fr> | 2020-01-21 07:45:47 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-01-21 07:46:04 +0100 |
commit | 4ad3644e185ff5fcbee7f2a9e419c463e67513b4 (patch) | |
tree | 37ba5c4bab126830c48d5f0bef90082180e6ddd7 /testsuite | |
parent | 2849ade7fc1ab10f73cf0be83a992b6e798ba087 (diff) | |
download | ghdl-4ad3644e185ff5fcbee7f2a9e419c463e67513b4.tar.gz ghdl-4ad3644e185ff5fcbee7f2a9e419c463e67513b4.tar.bz2 ghdl-4ad3644e185ff5fcbee7f2a9e419c463e67513b4.zip |
testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite')
-rw-r--r-- | testsuite/synth/synth80/test2.vhdl | 16 | ||||
-rwxr-xr-x | testsuite/synth/synth80/testsuite.sh | 1 |
2 files changed, 17 insertions, 0 deletions
diff --git a/testsuite/synth/synth80/test2.vhdl b/testsuite/synth/synth80/test2.vhdl new file mode 100644 index 000000000..473f67c74 --- /dev/null +++ b/testsuite/synth/synth80/test2.vhdl @@ -0,0 +1,16 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity testcase is + generic ( + init_bit : std_logic := '1' + ); + port (o : out std_logic_vector (2 downto 0)); +end testcase; + +architecture rtl of testcase is + -- assigning generic to multiple parts of std_logic_vector breaks ghdlsynth + signal test_assign_vector : std_logic_vector(2 downto 0) := init_bit & "0" & init_bit; +begin + o <= test_assign_vector; +end rtl; diff --git a/testsuite/synth/synth80/testsuite.sh b/testsuite/synth/synth80/testsuite.sh index 6d097693c..e0f9a4a18 100755 --- a/testsuite/synth/synth80/testsuite.sh +++ b/testsuite/synth/synth80/testsuite.sh @@ -3,6 +3,7 @@ . ../../testenv.sh synth testcase.vhdl -e > syn_testcase.vhdl +synth test2.vhdl -e > syn_test2.vhdl clean echo "Test successful" |