synth: also extract edge in PSL expressions.

2 files changed, 28 insertions, 1 deletions

diff --git a/testsuite/synth/psl01/assume2.vhdl b/testsuite/synth/psl01/assume2.vhdl
new file mode 100644
index 000000000..651d8f415
--- /dev/null
+++ b/testsuite/synth/psl01/assume2.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity assume2 is
+ port (clk, rst: std_logic;
+       cnt : out unsigned(3 downto 0));
+end assume2;
+
+architecture behav of assume2 is
+ signal val : unsigned (3 downto 0);
+begin
+ process(clk)
+ begin
+   if rising_edge(clk) then
+     if rst = '1' then
+       val <= (others => '0');
+     else
+       val <= val + 1;
+     end if;
+   end if;
+ end process;
+ cnt <= val;
+
+ --psl default clock is (clk'event and clk = '1');
+ --psl assume always val < 50;
+end behav;
diff --git a/testsuite/synth/psl01/testsuite.sh b/testsuite/synth/psl01/testsuite.sh
index 4c43382b6..3da284165 100755
--- a/testsuite/synth/psl01/testsuite.sh
+++ b/testsuite/synth/psl01/testsuite.sh
@@ -4,7 +4,7 @@
 
 GHDL_STD_FLAGS=--std=08
 
-for f in restrict1 assume1 assert1; do
+for f in restrict1 assume1 assume2 assert1; do
   synth -fpsl $f.vhdl -e $f > syn_$f.vhdl
   analyze syn_$f.vhdl
 done